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[SLP] Add X86 version of non-power-of-2 vectorization tests.
Extra X86 tests for #77790.
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‎llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=slp-vectorizer -mtriple=x86_64-apple-macosx -S %s | FileCheck %s
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define void @v3_load_i32_mul_by_constant_store(ptr %src, ptr %dst) {
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; CHECK-LABEL: @v3_load_i32_mul_by_constant_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 0
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; CHECK-NEXT: [[L_SRC_0:%.*]] = load i32, ptr [[GEP_SRC_0]], align 4
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; CHECK-NEXT: [[MUL_0:%.*]] = mul nsw i32 [[L_SRC_0]], 10
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; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 1
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; CHECK-NEXT: [[L_SRC_1:%.*]] = load i32, ptr [[GEP_SRC_1]], align 4
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; CHECK-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[L_SRC_1]], 10
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; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 2
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; CHECK-NEXT: [[L_SRC_2:%.*]] = load i32, ptr [[GEP_SRC_2]], align 4
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; CHECK-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[L_SRC_2]], 10
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; CHECK-NEXT: store i32 [[MUL_0]], ptr [[DST:%.*]], align 4
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; CHECK-NEXT: [[DST_1:%.*]] = getelementptr i32, ptr [[DST]], i32 1
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; CHECK-NEXT: store i32 [[MUL_1]], ptr [[DST_1]], align 4
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; CHECK-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST]], i32 2
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; CHECK-NEXT: store i32 [[MUL_2]], ptr [[DST_2]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%gep.src.0 = getelementptr inbounds i32, ptr %src, i32 0
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%l.src.0 = load i32, ptr %gep.src.0, align 4
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%mul.0 = mul nsw i32 %l.src.0, 10
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%gep.src.1 = getelementptr inbounds i32, ptr %src, i32 1
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%l.src.1 = load i32, ptr %gep.src.1, align 4
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%mul.1 = mul nsw i32 %l.src.1, 10
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%gep.src.2 = getelementptr inbounds i32, ptr %src, i32 2
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%l.src.2 = load i32, ptr %gep.src.2, align 4
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%mul.2 = mul nsw i32 %l.src.2, 10
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store i32 %mul.0, ptr %dst
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%dst.1 = getelementptr i32, ptr %dst, i32 1
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store i32 %mul.1, ptr %dst.1
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%dst.2 = getelementptr i32, ptr %dst, i32 2
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store i32 %mul.2, ptr %dst.2
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ret void
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}
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define void @v3_load_i32_mul_store(ptr %src.1, ptr %src.2, ptr %dst) {
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; CHECK-LABEL: @v3_load_i32_mul_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[GEP_SRC_1_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_1:%.*]], i32 0
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; CHECK-NEXT: [[L_SRC_1_0:%.*]] = load i32, ptr [[GEP_SRC_1_0]], align 4
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; CHECK-NEXT: [[GEP_SRC_2_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_2:%.*]], i32 0
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; CHECK-NEXT: [[L_SRC_2_0:%.*]] = load i32, ptr [[GEP_SRC_2_0]], align 4
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; CHECK-NEXT: [[MUL_0:%.*]] = mul nsw i32 [[L_SRC_1_0]], [[L_SRC_2_0]]
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; CHECK-NEXT: [[GEP_SRC_1_1:%.*]] = getelementptr inbounds i32, ptr [[SRC_1]], i32 1
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; CHECK-NEXT: [[L_SRC_1_1:%.*]] = load i32, ptr [[GEP_SRC_1_1]], align 4
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; CHECK-NEXT: [[GEP_SRC_2_1:%.*]] = getelementptr inbounds i32, ptr [[SRC_2]], i32 1
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; CHECK-NEXT: [[L_SRC_2_1:%.*]] = load i32, ptr [[GEP_SRC_2_1]], align 4
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; CHECK-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[L_SRC_1_1]], [[L_SRC_2_1]]
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; CHECK-NEXT: [[GEP_SRC_1_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_1]], i32 2
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; CHECK-NEXT: [[L_SRC_1_2:%.*]] = load i32, ptr [[GEP_SRC_1_2]], align 4
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; CHECK-NEXT: [[GEP_SRC_2_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_2]], i32 2
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; CHECK-NEXT: [[L_SRC_2_2:%.*]] = load i32, ptr [[GEP_SRC_2_2]], align 4
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; CHECK-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[L_SRC_1_2]], [[L_SRC_2_2]]
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; CHECK-NEXT: store i32 [[MUL_0]], ptr [[DST:%.*]], align 4
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; CHECK-NEXT: [[DST_1:%.*]] = getelementptr i32, ptr [[DST]], i32 1
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; CHECK-NEXT: store i32 [[MUL_1]], ptr [[DST_1]], align 4
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; CHECK-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST]], i32 2
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; CHECK-NEXT: store i32 [[MUL_2]], ptr [[DST_2]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%gep.src.1.0 = getelementptr inbounds i32, ptr %src.1, i32 0
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%l.src.1.0 = load i32, ptr %gep.src.1.0, align 4
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%gep.src.2.0 = getelementptr inbounds i32, ptr %src.2, i32 0
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%l.src.2.0 = load i32, ptr %gep.src.2.0, align 4
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%mul.0 = mul nsw i32 %l.src.1.0, %l.src.2.0
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%gep.src.1.1 = getelementptr inbounds i32, ptr %src.1, i32 1
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%l.src.1.1 = load i32, ptr %gep.src.1.1, align 4
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%gep.src.2.1 = getelementptr inbounds i32, ptr %src.2, i32 1
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%l.src.2.1 = load i32, ptr %gep.src.2.1, align 4
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%mul.1 = mul nsw i32 %l.src.1.1, %l.src.2.1
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%gep.src.1.2 = getelementptr inbounds i32, ptr %src.1, i32 2
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%l.src.1.2 = load i32, ptr %gep.src.1.2, align 4
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%gep.src.2.2 = getelementptr inbounds i32, ptr %src.2, i32 2
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%l.src.2.2 = load i32, ptr %gep.src.2.2, align 4
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%mul.2 = mul nsw i32 %l.src.1.2, %l.src.2.2
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store i32 %mul.0, ptr %dst
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%dst.1 = getelementptr i32, ptr %dst, i32 1
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store i32 %mul.1, ptr %dst.1
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%dst.2 = getelementptr i32, ptr %dst, i32 2
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store i32 %mul.2, ptr %dst.2
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ret void
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}
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define void @v3_load_i32_mul_add_const_store(ptr %src.1, ptr %src.2, ptr %dst) {
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; CHECK-LABEL: @v3_load_i32_mul_add_const_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[GEP_SRC_1_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_1:%.*]], i32 0
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; CHECK-NEXT: [[L_SRC_1_0:%.*]] = load i32, ptr [[GEP_SRC_1_0]], align 4
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; CHECK-NEXT: [[GEP_SRC_2_0:%.*]] = getelementptr inbounds i32, ptr [[SRC_2:%.*]], i32 0
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; CHECK-NEXT: [[L_SRC_2_0:%.*]] = load i32, ptr [[GEP_SRC_2_0]], align 4
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; CHECK-NEXT: [[MUL_0:%.*]] = mul nsw i32 [[L_SRC_1_0]], [[L_SRC_2_0]]
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; CHECK-NEXT: [[ADD_0:%.*]] = add i32 [[MUL_0]], 9
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; CHECK-NEXT: [[GEP_SRC_1_1:%.*]] = getelementptr inbounds i32, ptr [[SRC_1]], i32 1
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; CHECK-NEXT: [[L_SRC_1_1:%.*]] = load i32, ptr [[GEP_SRC_1_1]], align 4
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; CHECK-NEXT: [[GEP_SRC_2_1:%.*]] = getelementptr inbounds i32, ptr [[SRC_2]], i32 1
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; CHECK-NEXT: [[L_SRC_2_1:%.*]] = load i32, ptr [[GEP_SRC_2_1]], align 4
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; CHECK-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[L_SRC_1_1]], [[L_SRC_2_1]]
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; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[MUL_1]], 9
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; CHECK-NEXT: [[GEP_SRC_1_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_1]], i32 2
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; CHECK-NEXT: [[L_SRC_1_2:%.*]] = load i32, ptr [[GEP_SRC_1_2]], align 4
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; CHECK-NEXT: [[GEP_SRC_2_2:%.*]] = getelementptr inbounds i32, ptr [[SRC_2]], i32 2
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; CHECK-NEXT: [[L_SRC_2_2:%.*]] = load i32, ptr [[GEP_SRC_2_2]], align 4
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; CHECK-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[L_SRC_1_2]], [[L_SRC_2_2]]
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; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[MUL_2]], 9
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; CHECK-NEXT: store i32 [[ADD_0]], ptr [[DST:%.*]], align 4
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; CHECK-NEXT: [[DST_1:%.*]] = getelementptr i32, ptr [[DST]], i32 1
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; CHECK-NEXT: store i32 [[ADD_1]], ptr [[DST_1]], align 4
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; CHECK-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST]], i32 2
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; CHECK-NEXT: store i32 [[ADD_2]], ptr [[DST_2]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%gep.src.1.0 = getelementptr inbounds i32, ptr %src.1, i32 0
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%l.src.1.0 = load i32, ptr %gep.src.1.0, align 4
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%gep.src.2.0 = getelementptr inbounds i32, ptr %src.2, i32 0
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%l.src.2.0 = load i32, ptr %gep.src.2.0, align 4
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%mul.0 = mul nsw i32 %l.src.1.0, %l.src.2.0
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%add.0 = add i32 %mul.0, 9
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%gep.src.1.1 = getelementptr inbounds i32, ptr %src.1, i32 1
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%l.src.1.1 = load i32, ptr %gep.src.1.1, align 4
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%gep.src.2.1 = getelementptr inbounds i32, ptr %src.2, i32 1
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%l.src.2.1 = load i32, ptr %gep.src.2.1, align 4
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%mul.1 = mul nsw i32 %l.src.1.1, %l.src.2.1
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%add.1 = add i32 %mul.1, 9
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%gep.src.1.2 = getelementptr inbounds i32, ptr %src.1, i32 2
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%l.src.1.2 = load i32, ptr %gep.src.1.2, align 4
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%gep.src.2.2 = getelementptr inbounds i32, ptr %src.2, i32 2
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%l.src.2.2 = load i32, ptr %gep.src.2.2, align 4
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%mul.2 = mul nsw i32 %l.src.1.2, %l.src.2.2
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%add.2 = add i32 %mul.2, 9
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store i32 %add.0, ptr %dst
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%dst.1 = getelementptr i32, ptr %dst, i32 1
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store i32 %add.1, ptr %dst.1
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%dst.2 = getelementptr i32, ptr %dst, i32 2
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store i32 %add.2, ptr %dst.2
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ret void
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}
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define void @v3_load_f32_fadd_fadd_by_constant_store(ptr %src, ptr %dst) {
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; CHECK-LABEL: @v3_load_f32_fadd_fadd_by_constant_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds float, ptr [[SRC:%.*]], i32 0
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; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds float, ptr [[SRC]], i32 2
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; CHECK-NEXT: [[L_SRC_2:%.*]] = load float, ptr [[GEP_SRC_2]], align 4
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; CHECK-NEXT: [[FADD_2:%.*]] = fadd float [[L_SRC_2]], 1.000000e+01
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[GEP_SRC_0]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x float> [[TMP0]], <float 1.000000e+01, float 1.000000e+01>
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; CHECK-NEXT: store <2 x float> [[TMP1]], ptr [[DST:%.*]], align 4
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; CHECK-NEXT: [[DST_2:%.*]] = getelementptr float, ptr [[DST]], i32 2
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; CHECK-NEXT: store float [[FADD_2]], ptr [[DST_2]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%gep.src.0 = getelementptr inbounds float, ptr %src, i32 0
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%l.src.0 = load float , ptr %gep.src.0, align 4
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%fadd.0 = fadd float %l.src.0, 10.0
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%gep.src.1 = getelementptr inbounds float , ptr %src, i32 1
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%l.src.1 = load float, ptr %gep.src.1, align 4
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%fadd.1 = fadd float %l.src.1, 10.0
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%gep.src.2 = getelementptr inbounds float, ptr %src, i32 2
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%l.src.2 = load float, ptr %gep.src.2, align 4
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%fadd.2 = fadd float %l.src.2, 10.0
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store float %fadd.0, ptr %dst
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%dst.1 = getelementptr float, ptr %dst, i32 1
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store float %fadd.1, ptr %dst.1
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%dst.2 = getelementptr float, ptr %dst, i32 2
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store float %fadd.2, ptr %dst.2
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ret void
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}
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define void @phi_store3(ptr %dst) {
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; CHECK-LABEL: @phi_store3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: invoke.cont8.loopexit:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: [[P_2:%.*]] = phi i32 [ 3, [[ENTRY:%.*]] ], [ 0, [[INVOKE_CONT8_LOOPEXIT:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ <i32 1, i32 2>, [[ENTRY]] ], [ poison, [[INVOKE_CONT8_LOOPEXIT]] ]
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; CHECK-NEXT: [[DST_2:%.*]] = getelementptr i32, ptr [[DST:%.*]], i32 2
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; CHECK-NEXT: store <2 x i32> [[TMP0]], ptr [[DST]], align 4
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; CHECK-NEXT: store i32 [[P_2]], ptr [[DST_2]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br label %exit
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invoke.cont8.loopexit: ; No predecessors!
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br label %exit
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exit:
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%p.0 = phi i32 [ 1, %entry ], [ 0, %invoke.cont8.loopexit ]
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%p.1 = phi i32 [ 2, %entry ], [ 0, %invoke.cont8.loopexit ]
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%p.2 = phi i32 [ 3, %entry ], [ 0, %invoke.cont8.loopexit ]
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%dst.1 = getelementptr i32, ptr %dst, i32 1
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%dst.2 = getelementptr i32, ptr %dst, i32 2
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store i32 %p.0, ptr %dst, align 4
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store i32 %p.1, ptr %dst.1, align 4
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store i32 %p.2, ptr %dst.2, align 4
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ret void
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}
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define void @store_try_reorder(ptr %dst) {
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; CHECK-LABEL: @store_try_reorder(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ADD:%.*]] = add i32 0, 0
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; CHECK-NEXT: store i32 [[ADD]], ptr [[DST:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX_I1887:%.*]] = getelementptr i32, ptr [[DST]], i64 1
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; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[ARRAYIDX_I1887]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%add = add i32 0, 0
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store i32 %add, ptr %dst, align 4
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%add207 = sub i32 0, 0
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%arrayidx.i1887 = getelementptr i32, ptr %dst, i64 1
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store i32 %add207, ptr %arrayidx.i1887, align 4
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%add216 = sub i32 0, 0
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%arrayidx.i1891 = getelementptr i32, ptr %dst, i64 2
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store i32 %add216, ptr %arrayidx.i1891, align 4
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ret void
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}
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define void @vec3_fpext_cost(ptr %Colour, float %0) {
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; CHECK-LABEL: @vec3_fpext_cost(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = fpext <2 x float> [[TMP2]] to <2 x double>
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; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP3]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
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; CHECK-NEXT: [[TMP5:%.*]] = fptrunc <2 x double> [[TMP4]] to <2 x float>
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; CHECK-NEXT: store <2 x float> [[TMP5]], ptr [[COLOUR]], align 4
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; CHECK-NEXT: [[CONV78:%.*]] = fpext float [[TMP0]] to double
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; CHECK-NEXT: [[TMP6:%.*]] = call double @llvm.fmuladd.f64(double [[CONV78]], double 0.000000e+00, double 0.000000e+00)
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; CHECK-NEXT: [[CONV82:%.*]] = fptrunc double [[TMP6]] to float
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; CHECK-NEXT: store float [[CONV82]], ptr [[ARRAYIDX80]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%arrayidx72 = getelementptr float, ptr %Colour, i64 1
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%arrayidx80 = getelementptr float, ptr %Colour, i64 2
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%conv62 = fpext float %0 to double
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%1 = call double @llvm.fmuladd.f64(double %conv62, double 0.000000e+00, double 0.000000e+00)
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%conv66 = fptrunc double %1 to float
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store float %conv66, ptr %Colour, align 4
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%conv70 = fpext float %0 to double
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%2 = call double @llvm.fmuladd.f64(double %conv70, double 0.000000e+00, double 0.000000e+00)
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%conv74 = fptrunc double %2 to float
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store float %conv74, ptr %arrayidx72, align 4
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%conv78 = fpext float %0 to double
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%3 = call double @llvm.fmuladd.f64(double %conv78, double 0.000000e+00, double 0.000000e+00)
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%conv82 = fptrunc double %3 to float
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store float %conv82, ptr %arrayidx80, align 4
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ret void
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}
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define void @fpext_gather(ptr %dst, double %conv) {
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; CHECK-LABEL: @fpext_gather(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV:%.*]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
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; CHECK-NEXT: [[LENGTHS:%.*]] = getelementptr float, ptr [[DST:%.*]], i64 0
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
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; CHECK-NEXT: store float [[TMP3]], ptr [[LENGTHS]], align 4
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; CHECK-NEXT: [[ARRAYIDX32:%.*]] = getelementptr float, ptr [[DST]], i64 1
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; CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[ARRAYIDX32]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%conv25 = fptrunc double %conv to float
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%Lengths = getelementptr float, ptr %dst, i64 0
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store float %conv25, ptr %Lengths, align 4
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%arrayidx32 = getelementptr float, ptr %dst, i64 1
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store float %conv25, ptr %arrayidx32, align 4
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%conv34 = fptrunc double %conv to float
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%arrayidx37 = getelementptr float, ptr %dst, i64 2
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store float %conv34, ptr %arrayidx37, align 4
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ret void
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}
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declare float @llvm.fmuladd.f32(float, float, float)
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declare double @llvm.fmuladd.f64(double, double, double)

‎llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=slp-vectorizer -mtriple=x86_64-apple-macosx -S %s | FileCheck %s
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define void @vec3_vectorize_call(ptr %Colour, float %0) {
5+
; CHECK-LABEL: @vec3_vectorize_call(
6+
; CHECK-NEXT: entry:
7+
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[COLOUR:%.*]], align 4
8+
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP1]], <2 x float> zeroinitializer, <2 x float> zeroinitializer)
9+
; CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[COLOUR]], align 4
10+
; CHECK-NEXT: [[ARRAYIDX99_I1:%.*]] = getelementptr float, ptr [[COLOUR]], i64 2
11+
; CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.fmuladd.f32(float [[TMP0:%.*]], float 0.000000e+00, float 0.000000e+00)
12+
; CHECK-NEXT: store float [[TMP3]], ptr [[ARRAYIDX99_I1]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%1 = load float, ptr %Colour, align 4
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%2 = call float @llvm.fmuladd.f32(float %1, float 0.000000e+00, float 0.000000e+00)
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store float %2, ptr %Colour, align 4
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%arrayidx91.i = getelementptr float, ptr %Colour, i64 1
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%3 = load float, ptr %arrayidx91.i, align 4
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%4 = call float @llvm.fmuladd.f32(float %3, float 0.000000e+00, float 0.000000e+00)
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store float %4, ptr %arrayidx91.i, align 4
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%arrayidx99.i1 = getelementptr float, ptr %Colour, i64 2
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%5 = call float @llvm.fmuladd.f32(float %0, float 0.000000e+00, float 0.000000e+00)
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store float %5, ptr %arrayidx99.i1, align 4
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ret void
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}
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define void @vec3_fmuladd_64(ptr %Colour, double %0) {
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; CHECK-LABEL: @vec3_fmuladd_64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP2]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
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; CHECK-NEXT: [[TMP4:%.*]] = fptrunc <2 x double> [[TMP3]] to <2 x float>
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; CHECK-NEXT: store <2 x float> [[TMP4]], ptr [[COLOUR]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.fmuladd.f64(double [[TMP0]], double 0.000000e+00, double 0.000000e+00)
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; CHECK-NEXT: [[CONV82:%.*]] = fptrunc double [[TMP5]] to float
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; CHECK-NEXT: store float [[CONV82]], ptr [[ARRAYIDX80]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%arrayidx72 = getelementptr float, ptr %Colour, i64 1
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%arrayidx80 = getelementptr float, ptr %Colour, i64 2
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%1 = call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double 0.000000e+00)
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%conv66 = fptrunc double %1 to float
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store float %conv66, ptr %Colour, align 4
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%2 = call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double 0.000000e+00)
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%conv74 = fptrunc double %2 to float
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store float %conv74, ptr %arrayidx72, align 4
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%3 = call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double 0.000000e+00)
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%conv82 = fptrunc double %3 to float
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store float %conv82, ptr %arrayidx80, align 4
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ret void
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}
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declare float @llvm.fmuladd.f32(float, float, float)
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declare double @llvm.fmuladd.f64(double, double, double)

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