[AArch64][GlobalISel] Select TBL/TBX instrinsics

Author: chuongg3

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

@@ -227,6 +227,8 @@ class AArch64InstructionSelector : public InstructionSelector {
   bool selectReduction(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectMOPS(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectUSMovFromExtend(MachineInstr &I, MachineRegisterInfo &MRI);
+  void SelectTable(MachineInstr &I, MachineRegisterInfo &MRI, unsigned NumVecs,
+                   unsigned Opc, bool isExt);
 
   bool selectIndexedExtLoad(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectIndexedLoad(MachineInstr &I, MachineRegisterInfo &MRI);
@@ -6537,6 +6539,48 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
     I.eraseFromParent();
     return true;
   }
+  case Intrinsic::aarch64_neon_tbl2:
+    SelectTable(I, MRI, 2,
+                MRI.getType(I.getOperand(0).getReg()) == LLT::fixed_vector(8, 8)
+                    ? AArch64::TBLv8i8Two
+                    : AArch64::TBLv16i8Two,
+                false);
+    return true;
+  case Intrinsic::aarch64_neon_tbl3:
+    SelectTable(I, MRI, 3,
+                MRI.getType(I.getOperand(0).getReg()) == LLT::fixed_vector(8, 8)
+                    ? AArch64::TBLv8i8Three
+                    : AArch64::TBLv16i8Three,
+                false);
+    return true;
+  case Intrinsic::aarch64_neon_tbl4:
+    SelectTable(I, MRI, 4,
+                MRI.getType(I.getOperand(0).getReg()) == LLT::fixed_vector(8, 8)
+                    ? AArch64::TBLv8i8Four
+                    : AArch64::TBLv16i8Four,
+                false);
+    return true;
+  case Intrinsic::aarch64_neon_tbx2:
+    SelectTable(I, MRI, 2,
+                MRI.getType(I.getOperand(0).getReg()) == LLT::fixed_vector(8, 8)
+                    ? AArch64::TBXv8i8Two
+                    : AArch64::TBXv16i8Two,
+                true);
+    return true;
+  case Intrinsic::aarch64_neon_tbx3:
+    SelectTable(I, MRI, 3,
+                MRI.getType(I.getOperand(0).getReg()) == LLT::fixed_vector(8, 8)
+                    ? AArch64::TBXv8i8Three
+                    : AArch64::TBXv16i8Three,
+                true);
+    return true;
+  case Intrinsic::aarch64_neon_tbx4:
+    SelectTable(I, MRI, 4,
+                MRI.getType(I.getOperand(0).getReg()) == LLT::fixed_vector(8, 8)
+                    ? AArch64::TBXv8i8Four
+                    : AArch64::TBXv16i8Four,
+                true);
+    return true;
   case Intrinsic::swift_async_context_addr:
     auto Sub = MIB.buildInstr(AArch64::SUBXri, {I.getOperand(0).getReg()},
                               {Register(AArch64::FP)})
@@ -6552,6 +6596,28 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
   return false;
 }
 
+void AArch64InstructionSelector::SelectTable(MachineInstr &I,
+                                             MachineRegisterInfo &MRI,
+                                             unsigned NumVec, unsigned Opc,
+                                             bool isExt) {
+  // Create the REG_SEQUENCE
+  SmallVector<Register, 4> Regs;
+  for (unsigned i = 0; i < NumVec; i++)
+    Regs.push_back(I.getOperand(i + 2 + isExt).getReg());
+  Register RegSeq = createQTuple(Regs, MIB);
+
+  Register DstReg = I.getOperand(0).getReg();
+  Register IdxReg = I.getOperand(2 + NumVec + isExt).getReg();
+  MachineInstrBuilder Instr;
+  if (isExt) {
+    Register Reg = I.getOperand(2).getReg();
+    Instr = MIB.buildInstr(Opc, {DstReg}, {Reg, RegSeq, IdxReg});
+  } else
+    Instr = MIB.buildInstr(Opc, {DstReg}, {RegSeq, IdxReg});
+  constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI);
+  I.eraseFromParent();
+}
+
 InstructionSelector::ComplexRendererFns
 AArch64InstructionSelector::selectShiftA_32(const MachineOperand &Root) const {
   auto MaybeImmed = getImmedFromMO(Root);