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Commit 19a291f

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Jun Wang
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Modified the conditions for seeting both SrcBank and DstBank to
VCCRegBank in getInstrMapping(). Also created mir tests.
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2 files changed

+282
-13
lines changed

2 files changed

+282
-13
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 10 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3742,22 +3742,19 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
37423742
const RegisterBank *SrcBank = getRegBank(MI.getOperand(1).getReg(), MRI,
37433743
*TRI);
37443744
assert(SrcBank && "src bank should have been assigned already");
3745-
if (!DstBank)
3746-
DstBank = SrcBank;
37473745

3748-
// The calling convention is to be updated such that i1 function arguments
3749-
// or return values are assigned to SGPRs without promoting to i32. With
3750-
// this, for i1 function arguments, the call of getRegBank() above gives
3751-
// incorrect result. We set both src and dst banks to VCCRegBank.
3752-
if (!MI.getOperand(1).getReg().isVirtual() &&
3753-
MRI.getType(MI.getOperand(0).getReg()) == LLT::scalar(1)) {
3746+
// For copy from a physical reg to s1 dest, the call of getRegBank() above
3747+
// gives incorrect result. We set both src and dst banks to VCCRegBank.
3748+
if (!MI.getOperand(1).getReg().isVirtual() && !DstBank &&
3749+
MRI.getType(MI.getOperand(0).getReg()) == LLT::scalar(1))
3750+
DstBank = SrcBank = &AMDGPU::VCCRegBank;
3751+
// For copy from s1 src to a physical reg, we set both src and dst banks to
3752+
// VCCRegBank.
3753+
else if (!MI.getOperand(0).getReg().isVirtual() &&
3754+
MRI.getType(MI.getOperand(1).getReg()) == LLT::scalar(1))
37543755
DstBank = SrcBank = &AMDGPU::VCCRegBank;
3755-
}
37563756

3757-
// Similarly, for i1 return value, the dst reg is an SReg but we need to
3758-
// explicitly set the reg bank to VCCRegBank.
3759-
if (!MI.getOperand(0).getReg().isVirtual() &&
3760-
SrcBank == &AMDGPU::VCCRegBank)
3757+
if (!DstBank)
37613758
DstBank = SrcBank;
37623759

37633760
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir

Lines changed: 272 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,3 +201,275 @@ body: |
201201
%2:vcc(s1) = COPY %1
202202
S_ENDPGM 0, implicit %2
203203
...
204+
205+
---
206+
name: copy_sgpr_64_to_s1
207+
legalized: true
208+
209+
body: |
210+
bb.0:
211+
liveins: $sgpr4_sgpr5
212+
; CHECK-LABEL: name: copy_sgpr_64_to_s1
213+
; CHECK: liveins: $sgpr4_sgpr5
214+
; CHECK-NEXT: {{ $}}
215+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5
216+
; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
217+
; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
218+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]]
219+
%0:_(s1) = COPY $sgpr4_sgpr5
220+
%1:_(s32) = G_ZEXT %0:_(s1)
221+
...
222+
223+
---
224+
name: copy_sgpr_32_to_s1
225+
legalized: true
226+
227+
body: |
228+
bb.0:
229+
liveins: $sgpr0
230+
; CHECK-LABEL: name: copy_sgpr_32_to_s1
231+
; CHECK: liveins: $sgpr0
232+
; CHECK-NEXT: {{ $}}
233+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0
234+
; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
235+
; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
236+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]]
237+
%0:_(s1) = COPY $sgpr0
238+
%1:_(s32) = G_ZEXT %0:_(s1)
239+
...
240+
241+
---
242+
name: copy2_sgpr_64_to_s1
243+
legalized: true
244+
245+
body: |
246+
bb.0:
247+
liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
248+
; CHECK-LABEL: name: copy2_sgpr_64_to_s1
249+
; CHECK: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
250+
; CHECK-NEXT: {{ $}}
251+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5
252+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY $sgpr6_sgpr7
253+
; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
254+
; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
255+
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[CONST1]], [[CONST2]]
256+
; CHECK-NEXT: [[CONST3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
257+
; CHECK-NEXT: [[CONST4:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
258+
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[CONST3]], [[CONST4]]
259+
%0:_(s1) = COPY $sgpr4_sgpr5
260+
%1:_(s1) = COPY $sgpr6_sgpr7
261+
%2:_(s32) = G_ZEXT %0:_(s1)
262+
%3:_(s32) = G_ZEXT %1:_(s1)
263+
...
264+
265+
---
266+
name: copy2_sgpr_32_to_s1
267+
legalized: true
268+
269+
body: |
270+
bb.0:
271+
liveins: $sgpr0, $sgpr1
272+
; CHECK-LABEL: name: copy2_sgpr_32_to_s1
273+
; CHECK: liveins: $sgpr0, $sgpr1
274+
; CHECK-NEXT: {{ $}}
275+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr0
276+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY $sgpr1
277+
; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
278+
; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
279+
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[CONST1]], [[CONST2]]
280+
; CHECK-NEXT: [[CONST3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
281+
; CHECK-NEXT: [[CONST4:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
282+
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[CONST3]], [[CONST4]]
283+
%0:_(s1) = COPY $sgpr0
284+
%1:_(s1) = COPY $sgpr1
285+
%2:_(s32) = G_ZEXT %0:_(s1)
286+
%3:_(s32) = G_ZEXT %1:_(s1)
287+
...
288+
289+
---
290+
name: copy_sgpr_64_and_sgpr_32_to_s1
291+
legalized: true
292+
293+
body: |
294+
bb.0:
295+
liveins: $sgpr6, $sgpr4_sgpr5
296+
; CHECK-LABEL: name: copy_sgpr_64_and_sgpr_32_to_s1
297+
; CHECK: liveins: $sgpr6, $sgpr4_sgpr5
298+
; CHECK-NEXT: {{ $}}
299+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5
300+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
301+
; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
302+
; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
303+
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[CONST1]], [[CONST2]]
304+
; CHECK-NEXT: [[CONST3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
305+
; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[CONST3]]
306+
%0:_(s1) = COPY $sgpr4_sgpr5
307+
%2:_(s32) = COPY $sgpr6
308+
%7:_(s32) = G_ZEXT %0:_(s1)
309+
%5:_(s32) = G_CONSTANT i32 1
310+
%4:_(s32) = G_AND %2:_, %5:_
311+
...
312+
313+
---
314+
name: copy_sgpr_64_to_s1_vgpr
315+
legalized: true
316+
317+
body: |
318+
bb.0:
319+
liveins: $sgpr4_sgpr5
320+
; CHECK-LABEL: name: copy_sgpr_64_to_s1_vgpr
321+
; CHECK: liveins: $sgpr4_sgpr5
322+
; CHECK-NEXT: {{ $}}
323+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s1) = COPY $sgpr4_sgpr5
324+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vgpr(s32) = G_ZEXT [[COPY]](s1)
325+
%0:vgpr(s1) = COPY $sgpr4_sgpr5
326+
%1:_(s32) = G_ZEXT %0:vgpr(s1)
327+
...
328+
329+
---
330+
name: copy_sgpr_32_to_s1_vgpr
331+
legalized: true
332+
333+
body: |
334+
bb.0:
335+
liveins: $sgpr0
336+
; CHECK-LABEL: name: copy_sgpr_32_to_s1_vgpr
337+
; CHECK: liveins: $sgpr0
338+
; CHECK-NEXT: {{ $}}
339+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s1) = COPY $sgpr0
340+
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vgpr(s32) = G_ZEXT [[COPY]](s1)
341+
%0:vgpr(s1) = COPY $sgpr0
342+
%1:_(s32) = G_ZEXT %0:vgpr(s1)
343+
...
344+
345+
---
346+
name: copy_sgpr_64_to_s1_vcc
347+
legalized: true
348+
349+
body: |
350+
bb.0:
351+
liveins: $sgpr4_sgpr5
352+
; CHECK-LABEL: name: copy_sgpr_64_to_s1_vcc
353+
; CHECK: liveins: $sgpr4_sgpr5
354+
; CHECK-NEXT: {{ $}}
355+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5
356+
; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
357+
; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
358+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]]
359+
%0:vcc(s1) = COPY $sgpr4_sgpr5
360+
%1:_(s32) = G_ZEXT %0:vcc(s1)
361+
...
362+
363+
---
364+
name: copy_sgpr_32_to_s1_vcc
365+
legalized: true
366+
367+
body: |
368+
bb.0:
369+
liveins: $sgpr0
370+
; CHECK-LABEL: name: copy_sgpr_32_to_s1_vcc
371+
; CHECK: liveins: $sgpr0
372+
; CHECK-NEXT: {{ $}}
373+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0
374+
; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
375+
; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
376+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]]
377+
%0:vcc(s1) = COPY $sgpr0
378+
%1:_(s32) = G_ZEXT %0:vcc(s1)
379+
...
380+
381+
---
382+
name: copy_virt_reg_to_s1
383+
legalized: true
384+
385+
body: |
386+
bb.0:
387+
liveins: $vgpr0
388+
; CHECK-LABEL: name: copy_virt_reg_to_s1
389+
; CHECK: liveins: $vgpr0
390+
; CHECK-NEXT: {{ $}}
391+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
392+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
393+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1)
394+
%0:_(s32) = COPY $vgpr0
395+
%1:_(s1) = G_TRUNC %0
396+
%2:_(s1) = COPY %1
397+
...
398+
399+
---
400+
name: copy_virt_reg_to_s1_vgpr
401+
legalized: true
402+
403+
body: |
404+
bb.0:
405+
liveins: $vgpr0
406+
; CHECK-LABEL: name: copy_virt_reg_to_s1_vgpr
407+
; CHECK: liveins: $vgpr0
408+
; CHECK-NEXT: {{ $}}
409+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
410+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
411+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1)
412+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s1) = COPY [[COPY2]](s1)
413+
%0:_(s32) = COPY $vgpr0
414+
%1:_(s1) = G_TRUNC %0
415+
%2:vgpr(s1) = COPY %1
416+
%3:_(s1) = COPY %2
417+
...
418+
419+
420+
---
421+
name: copy_virt_reg_to_s1_vcc
422+
legalized: true
423+
424+
body: |
425+
bb.0:
426+
liveins: $vgpr0
427+
; CHECK-LABEL: name: copy_virt_reg_to_s1_vcc
428+
; CHECK: liveins: $vgpr0
429+
; CHECK-NEXT: {{ $}}
430+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
431+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
432+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
433+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[COPY2]](s1)
434+
%0:_(s32) = COPY $vgpr0
435+
%1:_(s1) = G_TRUNC %0
436+
%2:vcc(s1) = COPY %1
437+
%3:_(s1) = COPY %2
438+
...
439+
440+
---
441+
name: copy_s1_to_sgpr_64
442+
legalized: true
443+
444+
body: |
445+
bb.0:
446+
liveins: $vgpr0
447+
; CHECK-LABEL: name: copy_s1_to_sgpr_64
448+
; CHECK: liveins: $vgpr0
449+
; CHECK-NEXT: {{ $}}
450+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
451+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
452+
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[TRUNC]](s1)
453+
%0:_(s32) = COPY $vgpr0
454+
%1:_(s1) = G_TRUNC %0
455+
$sgpr4_sgpr5 = COPY %1
456+
...
457+
458+
---
459+
name: copy_s1_to_sgpr_32
460+
legalized: true
461+
462+
body: |
463+
bb.0:
464+
liveins: $vgpr0
465+
; CHECK-LABEL: name: copy_s1_to_sgpr_32
466+
; CHECK: liveins: $vgpr0
467+
; CHECK-NEXT: {{ $}}
468+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
469+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
470+
; CHECK-NEXT: $sgpr0 = COPY [[TRUNC]](s1)
471+
%0:_(s32) = COPY $vgpr0
472+
%1:_(s1) = G_TRUNC %0
473+
$sgpr0 = COPY %1
474+
...
475+

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