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fixup! don't use VLMaxSentinel
1 parent d58058e commit 1a23dc7

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2 files changed

+13
-9
lines changed

2 files changed

+13
-9
lines changed

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -840,7 +840,7 @@ buildDefaultVLOps(const DstOp &Dst, MachineIRBuilder &MIB,
840840
assert(VecTy.isScalableVector() && "Expecting scalable container type");
841841
const RISCVSubtarget &STI = MIB.getMF().getSubtarget<RISCVSubtarget>();
842842
LLT XLenTy(STI.getXLenVT());
843-
auto VL = MIB.buildConstant(XLenTy, RISCV::VLMaxSentinel);
843+
auto VL = MIB.buildConstant(XLenTy, -1);
844844
auto Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
845845
return {Mask, VL};
846846
}

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,10 @@ body: |
1717
;
1818
; NoF64-LABEL: name: splatvector_nxv1i64
1919
; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
20-
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
20+
; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
21+
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
2122
; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
22-
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], $x0
23+
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32)
2324
; NoF64-NEXT: $v8 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 1 x s64>)
2425
; NoF64-NEXT: PseudoRET implicit $v8
2526
%0:_(s64) = G_IMPLICIT_DEF
@@ -43,9 +44,10 @@ body: |
4344
;
4445
; NoF64-LABEL: name: splatvector_nxv2i64
4546
; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
46-
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
47+
; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
48+
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
4749
; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
48-
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], $x0
50+
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32)
4951
; NoF64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 2 x s64>)
5052
; NoF64-NEXT: PseudoRET implicit $v8m2
5153
%0:_(s64) = G_IMPLICIT_DEF
@@ -69,9 +71,10 @@ body: |
6971
;
7072
; NoF64-LABEL: name: splatvector_nxv4i64
7173
; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
72-
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
74+
; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
75+
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
7376
; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
74-
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], $x0
77+
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32)
7578
; NoF64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 4 x s64>)
7679
; NoF64-NEXT: PseudoRET implicit $v8m4
7780
%0:_(s64) = G_IMPLICIT_DEF
@@ -95,9 +98,10 @@ body: |
9598
;
9699
; NoF64-LABEL: name: splatvector_nxv8i64
97100
; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
98-
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
101+
; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
102+
; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
99103
; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
100-
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], $x0
104+
; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32)
101105
; NoF64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 8 x s64>)
102106
; NoF64-NEXT: PseudoRET implicit $v8m8
103107
%0:_(s64) = G_IMPLICIT_DEF

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