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AMDGPU: Add SourceOfDivergence for int_amdgcn_global_load_tr (#79218)
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‎llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td

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@@ -414,6 +414,7 @@ def : SourceOfDivergence<int_amdgcn_wmma_f16_16x16x16_f16>;
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def : SourceOfDivergence<int_amdgcn_wmma_bf16_16x16x16_bf16>;
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def : SourceOfDivergence<int_amdgcn_wmma_i32_16x16x16_iu8>;
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def : SourceOfDivergence<int_amdgcn_wmma_i32_16x16x16_iu4>;
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def : SourceOfDivergence<int_amdgcn_global_load_tr>;
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// The dummy boolean output is divergent from the IR's perspective,
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// but the mask results are uniform. These produce a divergent and

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll

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@@ -109,6 +109,78 @@ bb:
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call <2 x i32> @llvm.amdgcn.global.load.tr.v2i32(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b64_v2i32(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call <2 x i32> @llvm.amdgcn.global.load.tr.v2i32(ptr addrspace(1) %gep)
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store <2 x i32> %tmp0, ptr addrspace(1) %out, align 8
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call <8 x i16> @llvm.amdgcn.global.load.tr.v8i16(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b128_v8i16(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call <8 x i16> @llvm.amdgcn.global.load.tr.v8i16(ptr addrspace(1) %gep)
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store <8 x i16> %tmp0, ptr addrspace(1) %out, align 16
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call <8 x half> @llvm.amdgcn.global.load.tr.v8f16(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b128_v8f16(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call <8 x half> @llvm.amdgcn.global.load.tr.v8f16(ptr addrspace(1) %gep)
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store <8 x half> %tmp0, ptr addrspace(1) %out, align 16
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call <8 x bfloat> @llvm.amdgcn.global.load.tr.v8bf16(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b128_v8bf16(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call <8 x bfloat> @llvm.amdgcn.global.load.tr.v8bf16(ptr addrspace(1) %gep)
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store <8 x bfloat> %tmp0, ptr addrspace(1) %out, align 16
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.global.load.tr.i32(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b64_i32(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call i32 @llvm.amdgcn.global.load.tr.i32(ptr addrspace(1) %gep)
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store i32 %tmp0, ptr addrspace(1) %out, align 4
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call <4 x i16> @llvm.amdgcn.global.load.tr.v4i16(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b128_v4i16_(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call <4 x i16> @llvm.amdgcn.global.load.tr.v4i16(ptr addrspace(1) %gep)
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store <4 x i16> %tmp0, ptr addrspace(1) %out, align 8
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call <4 x half> @llvm.amdgcn.global.load.tr.v4f16(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b128_v4f16(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call <4 x half> @llvm.amdgcn.global.load.tr.v4f16(ptr addrspace(1) %gep)
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store <4 x half> %tmp0, ptr addrspace(1) %out, align 8
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call <4 x bfloat> @llvm.amdgcn.global.load.tr.v4bf16(ptr addrspace(1) %gep)
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define amdgpu_kernel void @global_load_tr_b128_v4bf16(ptr addrspace(1) %addr, ptr addrspace(1) %out) {
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bb:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%tmp0 = call <4 x bfloat> @llvm.amdgcn.global.load.tr.v4bf16(ptr addrspace(1) %gep)
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store <4 x bfloat> %tmp0, ptr addrspace(1) %out, align 8
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ret void
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}
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declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #1
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declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1) #1
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declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1) #1
@@ -125,5 +197,14 @@ declare <16 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v16i16(<16 x i16>, <16 x
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declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32(i1 immarg, <4 x i32>, i1 immarg, <4 x i32> , <8 x i32>, i1 immarg) #1
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declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32> , <8 x i32>, i1 immarg) #1
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declare <2 x i32> @llvm.amdgcn.global.load.tr.v2i32(ptr addrspace(1))
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declare <8 x i16> @llvm.amdgcn.global.load.tr.v8i16(ptr addrspace(1))
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declare <8 x half> @llvm.amdgcn.global.load.tr.v8f16(ptr addrspace(1))
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declare <8 x bfloat> @llvm.amdgcn.global.load.tr.v8bf16(ptr addrspace(1))
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declare i32 @llvm.amdgcn.global.load.tr.i32(ptr addrspace(1))
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declare <4 x i16> @llvm.amdgcn.global.load.tr.v4i16(ptr addrspace(1))
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declare <4 x half> @llvm.amdgcn.global.load.tr.v4f16(ptr addrspace(1))
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declare <4 x bfloat> @llvm.amdgcn.global.load.tr.v4bf16(ptr addrspace(1))
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attributes #0 = { nounwind convergent }
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attributes #1 = { nounwind readnone convergent }

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