@@ -2663,15 +2663,15 @@ LSRInstance::OptimizeLoopTermCond() {
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// Conservatively avoid trying to use the post-inc value in non-latch
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// exits if there may be pre-inc users in intervening blocks.
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if (LatchBlock != ExitingBlock)
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- for (IVUsers::const_iterator UI = IU. begin (), E = IU. end (); UI != E; ++UI )
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+ for (const IVStrideUse & UI : IU )
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// Test if the use is reachable from the exiting block. This dominator
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// query is a conservative approximation of reachability.
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- if (&* UI != CondUse &&
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- !DT.properlyDominates (UI-> getUser ()->getParent (), ExitingBlock)) {
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+ if (&UI != CondUse &&
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+ !DT.properlyDominates (UI. getUser ()->getParent (), ExitingBlock)) {
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// Conservatively assume there may be reuse if the quotient of their
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// strides could be a legal scale.
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const SCEV *A = IU.getStride (*CondUse, L);
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- const SCEV *B = IU.getStride (* UI, L);
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+ const SCEV *B = IU.getStride (UI, L);
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if (!A || !B) continue ;
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if (SE.getTypeSizeInBits (A->getType ()) !=
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SE.getTypeSizeInBits (B->getType ())) {
@@ -2692,9 +2692,9 @@ LSRInstance::OptimizeLoopTermCond() {
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C->getValue ().isMinSignedValue ())
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goto decline_post_inc;
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// Check for possible scaled-address reuse.
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- if (isAddressUse (TTI, UI-> getUser (), UI-> getOperandValToReplace ())) {
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- MemAccessTy AccessTy = getAccessType (
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- TTI, UI-> getUser (), UI-> getOperandValToReplace ());
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+ if (isAddressUse (TTI, UI. getUser (), UI. getOperandValToReplace ())) {
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+ MemAccessTy AccessTy =
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+ getAccessType ( TTI, UI. getUser (), UI. getOperandValToReplace ());
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int64_t Scale = C->getSExtValue ();
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if (TTI.isLegalAddressingMode (AccessTy.MemTy , /* BaseGV=*/ nullptr ,
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/* BaseOffset=*/ 0 ,
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