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[RISCV] Enable load clustering by default
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+9657
-9629
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -95,11 +95,6 @@ static cl::opt<bool>
9595
cl::desc("Enable Split RegisterAlloc for RVV"),
9696
cl::init(true));
9797

98-
static cl::opt<bool> EnableMISchedLoadClustering(
99-
"riscv-misched-load-clustering", cl::Hidden,
100-
cl::desc("Enable load clustering in the machine scheduler"),
101-
cl::init(false));
102-
10398
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
10499
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
105100
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@@ -345,15 +340,10 @@ class RISCVPassConfig : public TargetPassConfig {
345340
ScheduleDAGInstrs *
346341
createMachineScheduler(MachineSchedContext *C) const override {
347342
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
348-
ScheduleDAGMILive *DAG = nullptr;
349-
if (EnableMISchedLoadClustering) {
350-
DAG = createGenericSchedLive(C);
351-
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI, true));
352-
}
353-
if (ST.hasMacroFusion()) {
354-
DAG = DAG ? DAG : createGenericSchedLive(C);
343+
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
344+
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI, true));
345+
if (ST.hasMacroFusion())
355346
DAG->addMutation(createRISCVMacroFusionDAGMutation());
356-
}
357347
return DAG;
358348
}
359349

‎llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -63,15 +63,15 @@ define i32 @va1(ptr %fmt, ...) {
6363
; RV64-NEXT: sd a2, 32(sp)
6464
; RV64-NEXT: sd a3, 40(sp)
6565
; RV64-NEXT: sd a4, 48(sp)
66-
; RV64-NEXT: sd a5, 56(sp)
6766
; RV64-NEXT: addi a0, sp, 24
6867
; RV64-NEXT: sd a0, 8(sp)
69-
; RV64-NEXT: lw a0, 12(sp)
70-
; RV64-NEXT: lwu a1, 8(sp)
68+
; RV64-NEXT: lwu a0, 8(sp)
69+
; RV64-NEXT: lw a1, 12(sp)
70+
; RV64-NEXT: sd a5, 56(sp)
7171
; RV64-NEXT: sd a6, 64(sp)
7272
; RV64-NEXT: sd a7, 72(sp)
73-
; RV64-NEXT: slli a0, a0, 32
74-
; RV64-NEXT: or a0, a0, a1
73+
; RV64-NEXT: slli a1, a1, 32
74+
; RV64-NEXT: or a0, a1, a0
7575
; RV64-NEXT: addi a1, a0, 4
7676
; RV64-NEXT: srli a2, a1, 32
7777
; RV64-NEXT: sw a1, 8(sp)
@@ -968,22 +968,22 @@ define i32 @va_large_stack(ptr %fmt, ...) {
968968
; RV64-NEXT: add a0, sp, a0
969969
; RV64-NEXT: sd a4, 304(a0)
970970
; RV64-NEXT: lui a0, 24414
971-
; RV64-NEXT: add a0, sp, a0
972-
; RV64-NEXT: sd a5, 312(a0)
973-
; RV64-NEXT: lui a0, 24414
974971
; RV64-NEXT: addiw a0, a0, 280
975972
; RV64-NEXT: add a0, sp, a0
976973
; RV64-NEXT: sd a0, 8(sp)
977-
; RV64-NEXT: lw a0, 12(sp)
978-
; RV64-NEXT: lwu a1, 8(sp)
974+
; RV64-NEXT: lwu a0, 8(sp)
975+
; RV64-NEXT: lw a1, 12(sp)
976+
; RV64-NEXT: lui a2, 24414
977+
; RV64-NEXT: add a2, sp, a2
978+
; RV64-NEXT: sd a5, 312(a2)
979979
; RV64-NEXT: lui a2, 24414
980980
; RV64-NEXT: add a2, sp, a2
981981
; RV64-NEXT: sd a6, 320(a2)
982982
; RV64-NEXT: lui a2, 24414
983983
; RV64-NEXT: add a2, sp, a2
984984
; RV64-NEXT: sd a7, 328(a2)
985-
; RV64-NEXT: slli a0, a0, 32
986-
; RV64-NEXT: or a0, a0, a1
985+
; RV64-NEXT: slli a1, a1, 32
986+
; RV64-NEXT: or a0, a1, a0
987987
; RV64-NEXT: addi a1, a0, 4
988988
; RV64-NEXT: srli a2, a1, 32
989989
; RV64-NEXT: sw a1, 8(sp)

‎llvm/test/CodeGen/RISCV/add-before-shl.ll

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -167,17 +167,17 @@ define i128 @add_wide_operand(i128 %a) nounwind {
167167
; RV32I: # %bb.0:
168168
; RV32I-NEXT: lw a2, 0(a1)
169169
; RV32I-NEXT: lw a3, 4(a1)
170-
; RV32I-NEXT: lw a4, 12(a1)
171-
; RV32I-NEXT: lw a1, 8(a1)
170+
; RV32I-NEXT: lw a4, 8(a1)
171+
; RV32I-NEXT: lw a1, 12(a1)
172172
; RV32I-NEXT: srli a5, a2, 29
173173
; RV32I-NEXT: slli a6, a3, 3
174174
; RV32I-NEXT: or a5, a6, a5
175175
; RV32I-NEXT: srli a3, a3, 29
176-
; RV32I-NEXT: slli a6, a1, 3
176+
; RV32I-NEXT: slli a6, a4, 3
177177
; RV32I-NEXT: or a3, a6, a3
178-
; RV32I-NEXT: srli a1, a1, 29
179-
; RV32I-NEXT: slli a4, a4, 3
180-
; RV32I-NEXT: or a1, a4, a1
178+
; RV32I-NEXT: srli a4, a4, 29
179+
; RV32I-NEXT: slli a1, a1, 3
180+
; RV32I-NEXT: or a1, a1, a4
181181
; RV32I-NEXT: slli a2, a2, 3
182182
; RV32I-NEXT: lui a4, 128
183183
; RV32I-NEXT: add a1, a1, a4
@@ -200,26 +200,26 @@ define i128 @add_wide_operand(i128 %a) nounwind {
200200
;
201201
; RV32C-LABEL: add_wide_operand:
202202
; RV32C: # %bb.0:
203-
; RV32C-NEXT: lw a6, 4(a1)
204-
; RV32C-NEXT: c.lw a3, 12(a1)
205-
; RV32C-NEXT: c.lw a4, 0(a1)
203+
; RV32C-NEXT: c.lw a2, 12(a1)
204+
; RV32C-NEXT: lw a6, 0(a1)
205+
; RV32C-NEXT: c.lw a3, 4(a1)
206206
; RV32C-NEXT: c.lw a1, 8(a1)
207207
; RV32C-NEXT: c.lui a5, 16
208-
; RV32C-NEXT: c.add a3, a5
209-
; RV32C-NEXT: c.slli a3, 3
208+
; RV32C-NEXT: c.add a2, a5
209+
; RV32C-NEXT: c.slli a2, 3
210210
; RV32C-NEXT: srli a5, a1, 29
211-
; RV32C-NEXT: c.or a3, a5
212-
; RV32C-NEXT: srli a5, a4, 29
213-
; RV32C-NEXT: slli a2, a6, 3
214211
; RV32C-NEXT: c.or a2, a5
215212
; RV32C-NEXT: srli a5, a6, 29
213+
; RV32C-NEXT: slli a4, a3, 3
214+
; RV32C-NEXT: c.or a4, a5
215+
; RV32C-NEXT: c.srli a3, 29
216216
; RV32C-NEXT: c.slli a1, 3
217-
; RV32C-NEXT: c.or a1, a5
218-
; RV32C-NEXT: c.slli a4, 3
219-
; RV32C-NEXT: c.sw a4, 0(a0)
217+
; RV32C-NEXT: c.or a1, a3
218+
; RV32C-NEXT: c.slli a6, 3
219+
; RV32C-NEXT: sw a6, 0(a0)
220220
; RV32C-NEXT: c.sw a1, 8(a0)
221-
; RV32C-NEXT: c.sw a2, 4(a0)
222-
; RV32C-NEXT: c.sw a3, 12(a0)
221+
; RV32C-NEXT: c.sw a4, 4(a0)
222+
; RV32C-NEXT: c.sw a2, 12(a0)
223223
; RV32C-NEXT: c.jr ra
224224
;
225225
; RV64C-LABEL: add_wide_operand:

‎llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll

Lines changed: 52 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -192,37 +192,37 @@ define void @amomax_d_discard(ptr %a, i64 %b) nounwind {
192192
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
193193
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
194194
; RV32-NEXT: mv s0, a0
195-
; RV32-NEXT: lw a4, 4(a0)
196-
; RV32-NEXT: lw a5, 0(a0)
195+
; RV32-NEXT: lw a4, 0(a0)
196+
; RV32-NEXT: lw a5, 4(a0)
197197
; RV32-NEXT: mv s1, a2
198198
; RV32-NEXT: mv s2, a1
199199
; RV32-NEXT: j .LBB11_2
200200
; RV32-NEXT: .LBB11_1: # %atomicrmw.start
201201
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
202-
; RV32-NEXT: sw a5, 8(sp)
203-
; RV32-NEXT: sw a4, 12(sp)
202+
; RV32-NEXT: sw a4, 8(sp)
203+
; RV32-NEXT: sw a5, 12(sp)
204204
; RV32-NEXT: addi a1, sp, 8
205205
; RV32-NEXT: li a4, 5
206206
; RV32-NEXT: li a5, 5
207207
; RV32-NEXT: mv a0, s0
208208
; RV32-NEXT: call __atomic_compare_exchange_8@plt
209-
; RV32-NEXT: lw a4, 12(sp)
210-
; RV32-NEXT: lw a5, 8(sp)
209+
; RV32-NEXT: lw a4, 8(sp)
210+
; RV32-NEXT: lw a5, 12(sp)
211211
; RV32-NEXT: bnez a0, .LBB11_6
212212
; RV32-NEXT: .LBB11_2: # %atomicrmw.start
213213
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
214-
; RV32-NEXT: beq a4, s1, .LBB11_4
214+
; RV32-NEXT: beq a5, s1, .LBB11_4
215215
; RV32-NEXT: # %bb.3: # %atomicrmw.start
216216
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
217-
; RV32-NEXT: slt a0, s1, a4
218-
; RV32-NEXT: mv a2, a5
219-
; RV32-NEXT: mv a3, a4
217+
; RV32-NEXT: slt a0, s1, a5
218+
; RV32-NEXT: mv a2, a4
219+
; RV32-NEXT: mv a3, a5
220220
; RV32-NEXT: bnez a0, .LBB11_1
221221
; RV32-NEXT: j .LBB11_5
222222
; RV32-NEXT: .LBB11_4: # in Loop: Header=BB11_2 Depth=1
223-
; RV32-NEXT: sltu a0, s2, a5
224-
; RV32-NEXT: mv a2, a5
225-
; RV32-NEXT: mv a3, a4
223+
; RV32-NEXT: sltu a0, s2, a4
224+
; RV32-NEXT: mv a2, a4
225+
; RV32-NEXT: mv a3, a5
226226
; RV32-NEXT: bnez a0, .LBB11_1
227227
; RV32-NEXT: .LBB11_5: # %atomicrmw.start
228228
; RV32-NEXT: # in Loop: Header=BB11_2 Depth=1
@@ -268,37 +268,37 @@ define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind {
268268
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
269269
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
270270
; RV32-NEXT: mv s0, a0
271-
; RV32-NEXT: lw a4, 4(a0)
272-
; RV32-NEXT: lw a5, 0(a0)
271+
; RV32-NEXT: lw a4, 0(a0)
272+
; RV32-NEXT: lw a5, 4(a0)
273273
; RV32-NEXT: mv s1, a2
274274
; RV32-NEXT: mv s2, a1
275275
; RV32-NEXT: j .LBB13_2
276276
; RV32-NEXT: .LBB13_1: # %atomicrmw.start
277277
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
278-
; RV32-NEXT: sw a5, 8(sp)
279-
; RV32-NEXT: sw a4, 12(sp)
278+
; RV32-NEXT: sw a4, 8(sp)
279+
; RV32-NEXT: sw a5, 12(sp)
280280
; RV32-NEXT: addi a1, sp, 8
281281
; RV32-NEXT: li a4, 5
282282
; RV32-NEXT: li a5, 5
283283
; RV32-NEXT: mv a0, s0
284284
; RV32-NEXT: call __atomic_compare_exchange_8@plt
285-
; RV32-NEXT: lw a4, 12(sp)
286-
; RV32-NEXT: lw a5, 8(sp)
285+
; RV32-NEXT: lw a4, 8(sp)
286+
; RV32-NEXT: lw a5, 12(sp)
287287
; RV32-NEXT: bnez a0, .LBB13_6
288288
; RV32-NEXT: .LBB13_2: # %atomicrmw.start
289289
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
290-
; RV32-NEXT: beq a4, s1, .LBB13_4
290+
; RV32-NEXT: beq a5, s1, .LBB13_4
291291
; RV32-NEXT: # %bb.3: # %atomicrmw.start
292292
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
293-
; RV32-NEXT: sltu a0, s1, a4
294-
; RV32-NEXT: mv a2, a5
295-
; RV32-NEXT: mv a3, a4
293+
; RV32-NEXT: sltu a0, s1, a5
294+
; RV32-NEXT: mv a2, a4
295+
; RV32-NEXT: mv a3, a5
296296
; RV32-NEXT: bnez a0, .LBB13_1
297297
; RV32-NEXT: j .LBB13_5
298298
; RV32-NEXT: .LBB13_4: # in Loop: Header=BB13_2 Depth=1
299-
; RV32-NEXT: sltu a0, s2, a5
300-
; RV32-NEXT: mv a2, a5
301-
; RV32-NEXT: mv a3, a4
299+
; RV32-NEXT: sltu a0, s2, a4
300+
; RV32-NEXT: mv a2, a4
301+
; RV32-NEXT: mv a3, a5
302302
; RV32-NEXT: bnez a0, .LBB13_1
303303
; RV32-NEXT: .LBB13_5: # %atomicrmw.start
304304
; RV32-NEXT: # in Loop: Header=BB13_2 Depth=1
@@ -344,37 +344,37 @@ define void @amomin_d_discard(ptr %a, i64 %b) nounwind {
344344
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
345345
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
346346
; RV32-NEXT: mv s0, a0
347-
; RV32-NEXT: lw a4, 4(a0)
348-
; RV32-NEXT: lw a5, 0(a0)
347+
; RV32-NEXT: lw a4, 0(a0)
348+
; RV32-NEXT: lw a5, 4(a0)
349349
; RV32-NEXT: mv s1, a2
350350
; RV32-NEXT: mv s2, a1
351351
; RV32-NEXT: j .LBB15_2
352352
; RV32-NEXT: .LBB15_1: # %atomicrmw.start
353353
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
354-
; RV32-NEXT: sw a5, 8(sp)
355-
; RV32-NEXT: sw a4, 12(sp)
354+
; RV32-NEXT: sw a4, 8(sp)
355+
; RV32-NEXT: sw a5, 12(sp)
356356
; RV32-NEXT: addi a1, sp, 8
357357
; RV32-NEXT: li a4, 5
358358
; RV32-NEXT: li a5, 5
359359
; RV32-NEXT: mv a0, s0
360360
; RV32-NEXT: call __atomic_compare_exchange_8@plt
361-
; RV32-NEXT: lw a4, 12(sp)
362-
; RV32-NEXT: lw a5, 8(sp)
361+
; RV32-NEXT: lw a4, 8(sp)
362+
; RV32-NEXT: lw a5, 12(sp)
363363
; RV32-NEXT: bnez a0, .LBB15_6
364364
; RV32-NEXT: .LBB15_2: # %atomicrmw.start
365365
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
366-
; RV32-NEXT: beq a4, s1, .LBB15_4
366+
; RV32-NEXT: beq a5, s1, .LBB15_4
367367
; RV32-NEXT: # %bb.3: # %atomicrmw.start
368368
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
369-
; RV32-NEXT: slt a0, s1, a4
370-
; RV32-NEXT: mv a2, a5
371-
; RV32-NEXT: mv a3, a4
369+
; RV32-NEXT: slt a0, s1, a5
370+
; RV32-NEXT: mv a2, a4
371+
; RV32-NEXT: mv a3, a5
372372
; RV32-NEXT: beqz a0, .LBB15_1
373373
; RV32-NEXT: j .LBB15_5
374374
; RV32-NEXT: .LBB15_4: # in Loop: Header=BB15_2 Depth=1
375-
; RV32-NEXT: sltu a0, s2, a5
376-
; RV32-NEXT: mv a2, a5
377-
; RV32-NEXT: mv a3, a4
375+
; RV32-NEXT: sltu a0, s2, a4
376+
; RV32-NEXT: mv a2, a4
377+
; RV32-NEXT: mv a3, a5
378378
; RV32-NEXT: beqz a0, .LBB15_1
379379
; RV32-NEXT: .LBB15_5: # %atomicrmw.start
380380
; RV32-NEXT: # in Loop: Header=BB15_2 Depth=1
@@ -420,37 +420,37 @@ define void @amominu_d_discard(ptr %a, i64 %b) nounwind {
420420
; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
421421
; RV32-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
422422
; RV32-NEXT: mv s0, a0
423-
; RV32-NEXT: lw a4, 4(a0)
424-
; RV32-NEXT: lw a5, 0(a0)
423+
; RV32-NEXT: lw a4, 0(a0)
424+
; RV32-NEXT: lw a5, 4(a0)
425425
; RV32-NEXT: mv s1, a2
426426
; RV32-NEXT: mv s2, a1
427427
; RV32-NEXT: j .LBB17_2
428428
; RV32-NEXT: .LBB17_1: # %atomicrmw.start
429429
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1
430-
; RV32-NEXT: sw a5, 8(sp)
431-
; RV32-NEXT: sw a4, 12(sp)
430+
; RV32-NEXT: sw a4, 8(sp)
431+
; RV32-NEXT: sw a5, 12(sp)
432432
; RV32-NEXT: addi a1, sp, 8
433433
; RV32-NEXT: li a4, 5
434434
; RV32-NEXT: li a5, 5
435435
; RV32-NEXT: mv a0, s0
436436
; RV32-NEXT: call __atomic_compare_exchange_8@plt
437-
; RV32-NEXT: lw a4, 12(sp)
438-
; RV32-NEXT: lw a5, 8(sp)
437+
; RV32-NEXT: lw a4, 8(sp)
438+
; RV32-NEXT: lw a5, 12(sp)
439439
; RV32-NEXT: bnez a0, .LBB17_6
440440
; RV32-NEXT: .LBB17_2: # %atomicrmw.start
441441
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
442-
; RV32-NEXT: beq a4, s1, .LBB17_4
442+
; RV32-NEXT: beq a5, s1, .LBB17_4
443443
; RV32-NEXT: # %bb.3: # %atomicrmw.start
444444
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1
445-
; RV32-NEXT: sltu a0, s1, a4
446-
; RV32-NEXT: mv a2, a5
447-
; RV32-NEXT: mv a3, a4
445+
; RV32-NEXT: sltu a0, s1, a5
446+
; RV32-NEXT: mv a2, a4
447+
; RV32-NEXT: mv a3, a5
448448
; RV32-NEXT: beqz a0, .LBB17_1
449449
; RV32-NEXT: j .LBB17_5
450450
; RV32-NEXT: .LBB17_4: # in Loop: Header=BB17_2 Depth=1
451-
; RV32-NEXT: sltu a0, s2, a5
452-
; RV32-NEXT: mv a2, a5
453-
; RV32-NEXT: mv a3, a4
451+
; RV32-NEXT: sltu a0, s2, a4
452+
; RV32-NEXT: mv a2, a4
453+
; RV32-NEXT: mv a3, a5
454454
; RV32-NEXT: beqz a0, .LBB17_1
455455
; RV32-NEXT: .LBB17_5: # %atomicrmw.start
456456
; RV32-NEXT: # in Loop: Header=BB17_2 Depth=1

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