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[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)
This seems like an oversight when copying code from other backends.
1 parent cfe5a08 commit 1a935d7

14 files changed

+26
-27
lines changed

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3902,7 +3902,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
39023902
const TargetRegisterClass &RC = AArch64::GPR64RegClass;
39033903
unsigned Size = TRI->getSpillSize(RC);
39043904
Align Alignment = TRI->getSpillAlign(RC);
3905-
int FI = MFI.CreateStackObject(Size, Alignment, false);
3905+
int FI = MFI.CreateSpillStackObject(Size, Alignment);
39063906
RS->addScavengingFrameIndex(FI);
39073907
LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
39083908
<< " as the emergency spill slot.\n");

‎llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1438,7 +1438,7 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
14381438
// second VGPR emergency frame index.
14391439
if (HaveSGPRToVMemSpill &&
14401440
allocateScavengingFrameIndexesNearIncomingSP(MF)) {
1441-
RS->addScavengingFrameIndex(MFI.CreateStackObject(4, Align(4), false));
1441+
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(4, Align(4)));
14421442
}
14431443
}
14441444
}

‎llvm/lib/Target/ARC/ARCFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -438,8 +438,8 @@ void ARCFrameLowering::processFunctionBeforeFrameFinalized(
438438
LLVM_DEBUG(dbgs() << "Current stack size: " << MFI.getStackSize() << "\n");
439439
const TargetRegisterClass *RC = &ARC::GPR32RegClass;
440440
if (MFI.hasStackObjects()) {
441-
int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
442-
RegInfo->getSpillAlign(*RC), false);
441+
int RegScavFI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC),
442+
RegInfo->getSpillAlign(*RC));
443443
RS->addScavengingFrameIndex(RegScavFI);
444444
LLVM_DEBUG(dbgs() << "Created scavenging index RegScavFI=" << RegScavFI
445445
<< "\n");

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2925,7 +2925,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
29252925
unsigned Size = TRI->getSpillSize(RC);
29262926
Align Alignment = TRI->getSpillAlign(RC);
29272927
RS->addScavengingFrameIndex(
2928-
MFI.CreateStackObject(Size, Alignment, false));
2928+
MFI.CreateSpillStackObject(Size, Alignment));
29292929
--RegsNeeded;
29302930
}
29312931
}

‎llvm/lib/Target/CSKY/CSKYFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -441,7 +441,7 @@ void CSKYFrameLowering::determineCalleeSaves(MachineFunction &MF,
441441
unsigned size = TRI->getSpillSize(*RC);
442442
Align align = TRI->getSpillAlign(*RC);
443443

444-
RS->addScavengingFrameIndex(MFI.CreateStackObject(size, align, false));
444+
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(size, align));
445445
}
446446

447447
unsigned FnSize = EstimateFunctionSizeInBytes(MF, *TII);

‎llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -167,8 +167,8 @@ void LoongArchFrameLowering::processFunctionBeforeFrameFinalized(
167167

168168
// Create emergency spill slots.
169169
for (unsigned i = 0; i < ScavSlotsNum; ++i) {
170-
int FI = MFI.CreateStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC),
171-
false);
170+
int FI =
171+
MFI.CreateSpillStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC));
172172
RS->addScavengingFrameIndex(FI);
173173
if (IsLargeFunction && LAFI->getBranchRelaxationSpillFrameIndex() == -1)
174174
LAFI->setBranchRelaxationSpillFrameIndex(FI);

‎llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -892,8 +892,8 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
892892
// it should be 32-bit.
893893
const TargetRegisterClass &RC = STI.isGP64bit() ?
894894
Mips::GPR64RegClass : Mips::GPR32RegClass;
895-
int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
896-
TRI->getSpillAlign(RC), false);
895+
int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC),
896+
TRI->getSpillAlign(RC));
897897
RS->addScavengingFrameIndex(FI);
898898
}
899899

@@ -908,8 +908,8 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
908908

909909
const TargetRegisterClass &RC =
910910
ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;
911-
int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
912-
TRI->getSpillAlign(RC), false);
911+
int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC),
912+
TRI->getSpillAlign(RC));
913913
RS->addScavengingFrameIndex(FI);
914914
}
915915

‎llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2307,16 +2307,15 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
23072307
const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
23082308
unsigned Size = TRI.getSpillSize(RC);
23092309
Align Alignment = TRI.getSpillAlign(RC);
2310-
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false));
2310+
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));
23112311

23122312
// Might we have over-aligned allocas?
23132313
bool HasAlVars =
23142314
MFI.hasVarSizedObjects() && MFI.getMaxAlign() > getStackAlign();
23152315

23162316
// These kinds of spills might need two registers.
23172317
if (spillsCR(MF) || HasAlVars)
2318-
RS->addScavengingFrameIndex(
2319-
MFI.CreateStackObject(Size, Alignment, false));
2318+
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));
23202319
}
23212320
}
23222321

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1595,8 +1595,8 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
15951595
ScavSlotsNum = std::max(ScavSlotsNum, getScavSlotsNumForRVV(MF));
15961596

15971597
for (unsigned I = 0; I < ScavSlotsNum; I++) {
1598-
int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
1599-
RegInfo->getSpillAlign(*RC), false);
1598+
int FI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC),
1599+
RegInfo->getSpillAlign(*RC));
16001600
RS->addScavengingFrameIndex(FI);
16011601

16021602
if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)

‎llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -457,9 +457,9 @@ void SystemZELFFrameLowering::processFunctionBeforeFrameFinalized(
457457
// Create 2 for the case where both addresses in an MVC are
458458
// out of range.
459459
RS->addScavengingFrameIndex(
460-
MFFrame.CreateStackObject(getPointerSize(), Align(8), false));
460+
MFFrame.CreateSpillStackObject(getPointerSize(), Align(8)));
461461
RS->addScavengingFrameIndex(
462-
MFFrame.CreateStackObject(getPointerSize(), Align(8), false));
462+
MFFrame.CreateSpillStackObject(getPointerSize(), Align(8)));
463463
}
464464

465465
// If R6 is used as an argument register it is still callee saved. If it in
@@ -1491,8 +1491,8 @@ void SystemZXPLINKFrameLowering::processFunctionBeforeFrameFinalized(
14911491
if (!isUInt<12>(MaxReach)) {
14921492
// We may need register scavenging slots if some parts of the frame
14931493
// are outside the reach of an unsigned 12-bit displacement.
1494-
RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false));
1495-
RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false));
1494+
RS->addScavengingFrameIndex(MFFrame.CreateSpillStackObject(8, Align(8)));
1495+
RS->addScavengingFrameIndex(MFFrame.CreateSpillStackObject(8, Align(8)));
14961496
}
14971497
}
14981498

‎llvm/lib/Target/XCore/XCoreFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -576,7 +576,7 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF,
576576
unsigned Size = TRI.getSpillSize(RC);
577577
Align Alignment = TRI.getSpillAlign(RC);
578578
if (XFI->isLargeFrame(MF) || hasFP(MF))
579-
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false));
579+
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));
580580
if (XFI->isLargeFrame(MF) && !hasFP(MF))
581-
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false));
581+
RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment));
582582
}

‎llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,7 @@ void XtensaFrameLowering::processFunctionBeforeFrameFinalized(
276276
unsigned Size = TRI->getSpillSize(RC);
277277
Align Alignment = TRI->getSpillAlign(RC);
278278
for (unsigned I = 0; I < ScavSlotsNum; I++) {
279-
int FI = MFI.CreateStackObject(Size, Alignment, false);
279+
int FI = MFI.CreateSpillStackObject(Size, Alignment);
280280
RS->addScavengingFrameIndex(FI);
281281

282282
if (IsLargeFunction &&

‎llvm/test/CodeGen/PowerPC/alloca-crspill.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ declare signext i32 @do_something(ptr)
5353
; CHECK64-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
5454
; CHECK64-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '',
5555
; CHECK64-NEXT: debug-info-location: '' }
56-
; CHECK64-NEXT: - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
56+
; CHECK64-NEXT: - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
5757
; CHECK64-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
5858
; CHECK64-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
5959

@@ -72,7 +72,7 @@ declare signext i32 @do_something(ptr)
7272
; CHECK32-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
7373
; CHECK32-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '',
7474
; CHECK32-NEXT: debug-info-location: '' }
75-
; CHECK32-NEXT: - { id: 1, name: '', type: default, offset: -8, size: 4, alignment: 4,
75+
; CHECK32-NEXT: - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
7676
; CHECK32-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
7777
; CHECK32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
7878

‎llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ stack:
4040
- { id: 0, name: local0, type: default, offset: 0, size: 16, alignment: 16,
4141
stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
4242
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
43-
# CHECK: - { id: 2, name: '', type: default, offset: -16, size: 8, alignment: 8,
43+
# CHECK: - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
4444
# CHECK: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
4545
# CHECK: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
4646
callSites: []

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