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[RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.
Similar to what we do for add/sub/mul. This can help remove some sext.w. There are some regressions on some bswap tests, but I have an idea how to fix that for a follow up. A new PACKW pattern is added to handle the new sext_inreg placement. Differential Revision: https://reviews.llvm.org/D108663
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10 files changed

+113
-132
lines changed

10 files changed

+113
-132
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5060,9 +5060,26 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
50605060
case ISD::SRL:
50615061
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
50625062
"Unexpected custom legalisation");
5063-
if (N->getOperand(1).getOpcode() == ISD::Constant)
5064-
return;
5065-
Results.push_back(customLegalizeToWOp(N, DAG));
5063+
if (N->getOperand(1).getOpcode() != ISD::Constant) {
5064+
Results.push_back(customLegalizeToWOp(N, DAG));
5065+
break;
5066+
}
5067+
5068+
// Custom legalize ISD::SHL by placing a SIGN_EXTEND_INREG after. This is
5069+
// similar to customLegalizeToWOpWithSExt, but we must zero_extend the
5070+
// shift amount.
5071+
if (N->getOpcode() == ISD::SHL) {
5072+
SDLoc DL(N);
5073+
SDValue NewOp0 =
5074+
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
5075+
SDValue NewOp1 =
5076+
DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1));
5077+
SDValue NewWOp = DAG.getNode(ISD::SHL, DL, MVT::i64, NewOp0, NewOp1);
5078+
SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
5079+
DAG.getValueType(MVT::i32));
5080+
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes));
5081+
}
5082+
50665083
break;
50675084
case ISD::ROTL:
50685085
case ISD::ROTR:

‎llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1141,6 +1141,9 @@ def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
11411141
(and GPR:$rs1, 0x000000000000FFFF)),
11421142
i32)),
11431143
(PACKW GPR:$rs1, GPR:$rs2)>;
1144+
def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
1145+
(and GPR:$rs1, 0x000000000000FFFF))),
1146+
(PACKW GPR:$rs1, GPR:$rs2)>;
11441147
def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
11451148
(srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
11461149
(PACKUW GPR:$rs1, GPR:$rs2)>;

‎llvm/test/CodeGen/RISCV/alu32.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ define i32 @slli(i32 %a) nounwind {
106106
;
107107
; RV64I-LABEL: slli:
108108
; RV64I: # %bb.0:
109-
; RV64I-NEXT: slli a0, a0, 7
109+
; RV64I-NEXT: slliw a0, a0, 7
110110
; RV64I-NEXT: ret
111111
%1 = shl i32 %a, 7
112112
ret i32 %1

‎llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
6363
; RV64I-NEXT: slli a2, a0, 8
6464
; RV64I-NEXT: lui a3, 4080
6565
; RV64I-NEXT: and a2, a2, a3
66-
; RV64I-NEXT: slli a0, a0, 24
66+
; RV64I-NEXT: slliw a0, a0, 24
6767
; RV64I-NEXT: or a0, a0, a2
6868
; RV64I-NEXT: or a0, a0, a1
6969
; RV64I-NEXT: ret

‎llvm/test/CodeGen/RISCV/copysign-casts.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -205,9 +205,9 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
205205
; RV64I-NEXT: lui a2, 524288
206206
; RV64I-NEXT: addiw a2, a2, -1
207207
; RV64I-NEXT: and a0, a0, a2
208-
; RV64I-NEXT: lui a2, 1048568
208+
; RV64I-NEXT: lui a2, 8
209209
; RV64I-NEXT: and a1, a1, a2
210-
; RV64I-NEXT: slli a1, a1, 16
210+
; RV64I-NEXT: slliw a1, a1, 16
211211
; RV64I-NEXT: or a0, a0, a1
212212
; RV64I-NEXT: ret
213213
;

‎llvm/test/CodeGen/RISCV/mul.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -117,12 +117,12 @@ define i32 @mul_pow2(i32 %a) nounwind {
117117
;
118118
; RV64I-LABEL: mul_pow2:
119119
; RV64I: # %bb.0:
120-
; RV64I-NEXT: slli a0, a0, 3
120+
; RV64I-NEXT: slliw a0, a0, 3
121121
; RV64I-NEXT: ret
122122
;
123123
; RV64IM-LABEL: mul_pow2:
124124
; RV64IM: # %bb.0:
125-
; RV64IM-NEXT: slli a0, a0, 3
125+
; RV64IM-NEXT: slliw a0, a0, 3
126126
; RV64IM-NEXT: ret
127127
%1 = mul i32 %a, 8
128128
ret i32 %1

‎llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1422,7 +1422,7 @@ define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
14221422
define i32 @aext_slliw_aext(i32 %a) nounwind {
14231423
; RV64I-LABEL: aext_slliw_aext:
14241424
; RV64I: # %bb.0:
1425-
; RV64I-NEXT: slli a0, a0, 1
1425+
; RV64I-NEXT: slliw a0, a0, 1
14261426
; RV64I-NEXT: ret
14271427
%1 = shl i32 %a, 1
14281428
ret i32 %1
@@ -1431,7 +1431,7 @@ define i32 @aext_slliw_aext(i32 %a) nounwind {
14311431
define i32 @aext_slliw_sext(i32 signext %a) nounwind {
14321432
; RV64I-LABEL: aext_slliw_sext:
14331433
; RV64I: # %bb.0:
1434-
; RV64I-NEXT: slli a0, a0, 2
1434+
; RV64I-NEXT: slliw a0, a0, 2
14351435
; RV64I-NEXT: ret
14361436
%1 = shl i32 %a, 2
14371437
ret i32 %1
@@ -1440,7 +1440,7 @@ define i32 @aext_slliw_sext(i32 signext %a) nounwind {
14401440
define i32 @aext_slliw_zext(i32 zeroext %a) nounwind {
14411441
; RV64I-LABEL: aext_slliw_zext:
14421442
; RV64I: # %bb.0:
1443-
; RV64I-NEXT: slli a0, a0, 3
1443+
; RV64I-NEXT: slliw a0, a0, 3
14441444
; RV64I-NEXT: ret
14451445
%1 = shl i32 %a, 3
14461446
ret i32 %1

‎llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -412,9 +412,8 @@ define signext i32 @rori_i32_fshl(i32 signext %a) nounwind {
412412
; RV64I-LABEL: rori_i32_fshl:
413413
; RV64I: # %bb.0:
414414
; RV64I-NEXT: srliw a1, a0, 1
415-
; RV64I-NEXT: slli a0, a0, 31
415+
; RV64I-NEXT: slliw a0, a0, 31
416416
; RV64I-NEXT: or a0, a0, a1
417-
; RV64I-NEXT: sext.w a0, a0
418417
; RV64I-NEXT: ret
419418
;
420419
; RV64B-LABEL: rori_i32_fshl:
@@ -470,10 +469,9 @@ define void @rori_i32_fshl_nosext(i32 signext %a, i32* %x) nounwind {
470469
define signext i32 @rori_i32_fshr(i32 signext %a) nounwind {
471470
; RV64I-LABEL: rori_i32_fshr:
472471
; RV64I: # %bb.0:
473-
; RV64I-NEXT: slli a1, a0, 1
472+
; RV64I-NEXT: slliw a1, a0, 1
474473
; RV64I-NEXT: srliw a0, a0, 31
475474
; RV64I-NEXT: or a0, a0, a1
476-
; RV64I-NEXT: sext.w a0, a0
477475
; RV64I-NEXT: ret
478476
;
479477
; RV64B-LABEL: rori_i32_fshr:
@@ -532,34 +530,30 @@ define void @rori_i32_fshr_nosext(i32 signext %a, i32* %x) nounwind {
532530
define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind {
533531
; RV64I-LABEL: not_rori_i32:
534532
; RV64I: # %bb.0:
535-
; RV64I-NEXT: slli a0, a0, 31
533+
; RV64I-NEXT: slliw a0, a0, 31
536534
; RV64I-NEXT: srliw a1, a1, 1
537535
; RV64I-NEXT: or a0, a0, a1
538-
; RV64I-NEXT: sext.w a0, a0
539536
; RV64I-NEXT: ret
540537
;
541538
; RV64B-LABEL: not_rori_i32:
542539
; RV64B: # %bb.0:
543-
; RV64B-NEXT: slli a0, a0, 31
540+
; RV64B-NEXT: slliw a0, a0, 31
544541
; RV64B-NEXT: srliw a1, a1, 1
545542
; RV64B-NEXT: or a0, a0, a1
546-
; RV64B-NEXT: sext.w a0, a0
547543
; RV64B-NEXT: ret
548544
;
549545
; RV64ZBB-LABEL: not_rori_i32:
550546
; RV64ZBB: # %bb.0:
551-
; RV64ZBB-NEXT: slli a0, a0, 31
547+
; RV64ZBB-NEXT: slliw a0, a0, 31
552548
; RV64ZBB-NEXT: srliw a1, a1, 1
553549
; RV64ZBB-NEXT: or a0, a0, a1
554-
; RV64ZBB-NEXT: sext.w a0, a0
555550
; RV64ZBB-NEXT: ret
556551
;
557552
; RV64ZBP-LABEL: not_rori_i32:
558553
; RV64ZBP: # %bb.0:
559-
; RV64ZBP-NEXT: slli a0, a0, 31
554+
; RV64ZBP-NEXT: slliw a0, a0, 31
560555
; RV64ZBP-NEXT: srliw a1, a1, 1
561556
; RV64ZBP-NEXT: or a0, a0, a1
562-
; RV64ZBP-NEXT: sext.w a0, a0
563557
; RV64ZBP-NEXT: ret
564558
%a = shl i32 %x, 31
565559
%b = lshr i32 %y, 1

‎llvm/test/CodeGen/RISCV/rv64zbb.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1515,10 +1515,9 @@ define signext i32 @bswap_i32(i32 signext %a) nounwind {
15151515
; RV64I-NEXT: slli a2, a0, 8
15161516
; RV64I-NEXT: lui a3, 4080
15171517
; RV64I-NEXT: and a2, a2, a3
1518-
; RV64I-NEXT: slli a0, a0, 24
1518+
; RV64I-NEXT: slliw a0, a0, 24
15191519
; RV64I-NEXT: or a0, a0, a2
15201520
; RV64I-NEXT: or a0, a0, a1
1521-
; RV64I-NEXT: sext.w a0, a0
15221521
; RV64I-NEXT: ret
15231522
;
15241523
; RV64B-LABEL: bswap_i32:

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