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[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
If the source is implicit_def, the register allocator won't have any constraint on what register it picks for the destination. This doesn't give the user much control of what register is being used. So in my mind that means the only reason to honor the policy operand is to control what policy is used in vsetvli to maybe avoid a vtype change. Given the other optimizations we do on the policy field, I don't think allowing the user this control is reliable. Therefore, I think we should use agnostic policies if the source is undef. This should give better performance on some CPUs for VP intrinsics where there is no merge operand and the backend adds IMPLICIT_DEF to the instruction. Differential Revision: https://reviews.llvm.org/D135396
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‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 24 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -768,28 +768,25 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
768768
const MachineRegisterInfo *MRI) {
769769
VSETVLIInfo InstrInfo;
770770

771-
// If the instruction has policy argument, use the argument.
772-
// If there is no policy argument, default to tail agnostic unless the
773-
// destination is tied to a source. Unless the source is undef. In that case
774-
// the user would have some control over the policy values.
775-
bool TailAgnostic = true;
776-
bool MaskAgnostic = true;
771+
bool TailAgnostic, MaskAgnostic;
777772
unsigned UseOpIdx;
778-
if (RISCVII::hasVecPolicyOp(TSFlags)) {
779-
const MachineOperand &Op = MI.getOperand(MI.getNumExplicitOperands() - 1);
780-
uint64_t Policy = Op.getImm();
781-
assert(Policy <= (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC) &&
782-
"Invalid Policy Value");
783-
// Although in some cases, mismatched passthru/maskedoff with policy value
784-
// does not make sense (ex. tied operand is IMPLICIT_DEF with non-TAMA
785-
// policy, or tied operand is not IMPLICIT_DEF with TAMA policy), but users
786-
// have set the policy value explicitly, so compiler would not fix it.
787-
TailAgnostic = Policy & RISCVII::TAIL_AGNOSTIC;
788-
MaskAgnostic = Policy & RISCVII::MASK_AGNOSTIC;
789-
} else if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
773+
if (MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
774+
// Start with undisturbed.
790775
TailAgnostic = false;
791776
MaskAgnostic = false;
792-
// If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
777+
778+
// If there is a policy operand, use it.
779+
if (RISCVII::hasVecPolicyOp(TSFlags)) {
780+
const MachineOperand &Op = MI.getOperand(MI.getNumExplicitOperands() - 1);
781+
uint64_t Policy = Op.getImm();
782+
assert(Policy <= (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC) &&
783+
"Invalid Policy Value");
784+
TailAgnostic = Policy & RISCVII::TAIL_AGNOSTIC;
785+
MaskAgnostic = Policy & RISCVII::MASK_AGNOSTIC;
786+
}
787+
788+
// If the tied operand is an IMPLICIT_DEF we can use TailAgnostic and
789+
// MaskAgnostic.
793790
const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
794791
MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
795792
if (UseMI && UseMI->isImplicitDef()) {
@@ -800,10 +797,16 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
800797
// tied def.
801798
if (RISCVII::doesForceTailAgnostic(TSFlags))
802799
TailAgnostic = true;
803-
}
804800

805-
if (!RISCVII::usesMaskPolicy(TSFlags))
801+
if (!RISCVII::usesMaskPolicy(TSFlags))
802+
MaskAgnostic = true;
803+
} else {
804+
// If there is no tied operand,, there shouldn't be a policy operand.
805+
assert(!RISCVII::hasVecPolicyOp(TSFlags) && "Unexpected policy operand");
806+
// No tied operand use agnostic policies.
807+
TailAgnostic = true;
806808
MaskAgnostic = true;
809+
}
807810

808811
RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags);
809812

‎llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ define void @last_chance_recoloring_failure() {
3838
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
3939
; CHECK-NEXT: vmclr.m v0
4040
; CHECK-NEXT: li s0, 36
41-
; CHECK-NEXT: vsetvli zero, s0, e16, m4, tu, mu
41+
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
4242
; CHECK-NEXT: vfwadd.vv v8, v8, v8, v0.t
4343
; CHECK-NEXT: csrr a0, vlenb
4444
; CHECK-NEXT: slli a0, a0, 4
@@ -47,7 +47,7 @@ define void @last_chance_recoloring_failure() {
4747
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
4848
; CHECK-NEXT: call func@plt
4949
; CHECK-NEXT: li a0, 32
50-
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
50+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
5151
; CHECK-NEXT: vrgather.vv v4, v8, v8, v0.t
5252
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
5353
; CHECK-NEXT: csrr a1, vlenb
@@ -114,13 +114,13 @@ define void @last_chance_recoloring_failure() {
114114
; SUBREGLIVENESS-NEXT: vsetvli a0, zero, e8, m2, ta, ma
115115
; SUBREGLIVENESS-NEXT: vmclr.m v0
116116
; SUBREGLIVENESS-NEXT: li s0, 36
117-
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, tu, mu
117+
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
118118
; SUBREGLIVENESS-NEXT: vfwadd.vv v8, v8, v8, v0.t
119119
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
120120
; SUBREGLIVENESS-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
121121
; SUBREGLIVENESS-NEXT: call func@plt
122122
; SUBREGLIVENESS-NEXT: li a0, 32
123-
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, tu, mu
123+
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
124124
; SUBREGLIVENESS-NEXT: vrgather.vv v16, v8, v8, v0.t
125125
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
126126
; SUBREGLIVENESS-NEXT: csrr a1, vlenb

‎llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp-mask.ll

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,8 @@ declare <2 x i1> @llvm.vp.trunc.v2i1.v2i16(<2 x i16>, <2 x i1>, i32)
77
define <2 x i1> @vtrunc_v2i1_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
88
; CHECK-LABEL: vtrunc_v2i1_v2i16:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
10+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1111
; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
12-
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1312
; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
1413
; CHECK-NEXT: ret
1514
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
@@ -32,9 +31,8 @@ declare <2 x i1> @llvm.vp.trunc.v2i1.v2i32(<2 x i32>, <2 x i1>, i32)
3231
define <2 x i1> @vtrunc_v2i1_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
3332
; CHECK-LABEL: vtrunc_v2i1_v2i32:
3433
; CHECK: # %bb.0:
35-
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
34+
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
3635
; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
37-
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
3836
; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
3937
; CHECK-NEXT: ret
4038
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
@@ -57,9 +55,8 @@ declare <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64>, <2 x i1>, i32)
5755
define <2 x i1> @vtrunc_v2i1_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
5856
; CHECK-LABEL: vtrunc_v2i1_v2i64:
5957
; CHECK: # %bb.0:
60-
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
58+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
6159
; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
62-
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
6360
; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
6461
; CHECK-NEXT: ret
6562
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -511,7 +511,7 @@ define <4 x i16> @bitcast_i64_v4i16(i64 %a) {
511511
; RV32-NEXT: vmv.v.i v8, 0
512512
; RV32-NEXT: vslide1up.vx v9, v8, a1
513513
; RV32-NEXT: vslide1up.vx v10, v9, a0
514-
; RV32-NEXT: vsetivli zero, 1, e64, m1, tu, ma
514+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
515515
; RV32-NEXT: vslideup.vi v8, v10, 0
516516
; RV32-NEXT: ret
517517
;
@@ -550,7 +550,7 @@ define <2 x i32> @bitcast_i64_v2i32(i64 %a) {
550550
; RV32-NEXT: vmv.v.i v8, 0
551551
; RV32-NEXT: vslide1up.vx v9, v8, a1
552552
; RV32-NEXT: vslide1up.vx v10, v9, a0
553-
; RV32-NEXT: vsetivli zero, 1, e64, m1, tu, ma
553+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
554554
; RV32-NEXT: vslideup.vi v8, v10, 0
555555
; RV32-NEXT: ret
556556
;
@@ -589,7 +589,7 @@ define <1 x i64> @bitcast_i64_v1i64(i64 %a) {
589589
; RV32-NEXT: vmv.v.i v8, 0
590590
; RV32-NEXT: vslide1up.vx v9, v8, a1
591591
; RV32-NEXT: vslide1up.vx v10, v9, a0
592-
; RV32-NEXT: vsetivli zero, 1, e64, m1, tu, ma
592+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
593593
; RV32-NEXT: vslideup.vi v8, v10, 0
594594
; RV32-NEXT: ret
595595
;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ define <4 x half> @bitcast_i64_v4f16(i64 %a) {
202202
; RV32-FP-NEXT: vmv.v.i v8, 0
203203
; RV32-FP-NEXT: vslide1up.vx v9, v8, a1
204204
; RV32-FP-NEXT: vslide1up.vx v10, v9, a0
205-
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, tu, ma
205+
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma
206206
; RV32-FP-NEXT: vslideup.vi v8, v10, 0
207207
; RV32-FP-NEXT: ret
208208
;
@@ -222,7 +222,7 @@ define <2 x float> @bitcast_i64_v2f32(i64 %a) {
222222
; RV32-FP-NEXT: vmv.v.i v8, 0
223223
; RV32-FP-NEXT: vslide1up.vx v9, v8, a1
224224
; RV32-FP-NEXT: vslide1up.vx v10, v9, a0
225-
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, tu, ma
225+
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma
226226
; RV32-FP-NEXT: vslideup.vi v8, v10, 0
227227
; RV32-FP-NEXT: ret
228228
;
@@ -242,7 +242,7 @@ define <1 x double> @bitcast_i64_v1f64(i64 %a) {
242242
; RV32-FP-NEXT: vmv.v.i v8, 0
243243
; RV32-FP-NEXT: vslide1up.vx v9, v8, a1
244244
; RV32-FP-NEXT: vslide1up.vx v10, v9, a0
245-
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, tu, ma
245+
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, ma
246246
; RV32-FP-NEXT: vslideup.vi v8, v10, 0
247247
; RV32-FP-NEXT: ret
248248
;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ define <8 x float> @slidedown_v8f32(<8 x float> %x) {
249249
define <4 x half> @slideup_v4f16(<4 x half> %x) {
250250
; CHECK-LABEL: slideup_v4f16:
251251
; CHECK: # %bb.0:
252-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma
252+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
253253
; CHECK-NEXT: vslideup.vi v9, v8, 1
254254
; CHECK-NEXT: vmv1r.v v8, v9
255255
; CHECK-NEXT: ret
@@ -260,9 +260,9 @@ define <4 x half> @slideup_v4f16(<4 x half> %x) {
260260
define <8 x float> @slideup_v8f32(<8 x float> %x) {
261261
; CHECK-LABEL: slideup_v8f32:
262262
; CHECK: # %bb.0:
263-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma
263+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
264264
; CHECK-NEXT: vslideup.vi v10, v8, 3
265-
; CHECK-NEXT: vmv2r.v v8, v10
265+
; CHECK-NEXT: vmv.v.v v8, v10
266266
; CHECK-NEXT: ret
267267
%s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
268268
ret <8 x float> %s

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -256,7 +256,7 @@ define void @insert_v8i32_undef_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
256256
; LMULMAX2: # %bb.0:
257257
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
258258
; LMULMAX2-NEXT: vle32.v v8, (a1)
259-
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, tu, ma
259+
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
260260
; LMULMAX2-NEXT: vslideup.vi v10, v8, 6
261261
; LMULMAX2-NEXT: vse32.v v10, (a0)
262262
; LMULMAX2-NEXT: ret
@@ -265,7 +265,7 @@ define void @insert_v8i32_undef_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
265265
; LMULMAX1: # %bb.0:
266266
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
267267
; LMULMAX1-NEXT: vle32.v v8, (a1)
268-
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, ma
268+
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
269269
; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
270270
; LMULMAX1-NEXT: addi a0, a0, 16
271271
; LMULMAX1-NEXT: vse32.v v9, (a0)
@@ -544,7 +544,7 @@ define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %ou
544544
; CHECK: # %bb.0:
545545
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
546546
; CHECK-NEXT: vle64.v v8, (a0)
547-
; CHECK-NEXT: vsetivli zero, 4, e64, m8, tu, ma
547+
; CHECK-NEXT: vsetivli zero, 4, e64, m8, ta, ma
548548
; CHECK-NEXT: vslideup.vi v16, v8, 2
549549
; CHECK-NEXT: vs8r.v v16, (a1)
550550
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -538,7 +538,7 @@ define <8 x i32> @slidedown_v8i32(<8 x i32> %x) {
538538
define <4 x i16> @slideup_v4i16(<4 x i16> %x) {
539539
; CHECK-LABEL: slideup_v4i16:
540540
; CHECK: # %bb.0:
541-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma
541+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
542542
; CHECK-NEXT: vslideup.vi v9, v8, 1
543543
; CHECK-NEXT: vmv1r.v v8, v9
544544
; CHECK-NEXT: ret
@@ -549,9 +549,9 @@ define <4 x i16> @slideup_v4i16(<4 x i16> %x) {
549549
define <8 x i32> @slideup_v8i32(<8 x i32> %x) {
550550
; CHECK-LABEL: slideup_v8i32:
551551
; CHECK: # %bb.0:
552-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma
552+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
553553
; CHECK-NEXT: vslideup.vi v10, v8, 3
554-
; CHECK-NEXT: vmv2r.v v8, v10
554+
; CHECK-NEXT: vmv.v.v v8, v10
555555
; CHECK-NEXT: ret
556556
%s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
557557
ret <8 x i32> %s

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