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AZero13AZero13
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[InstCombine] Pre-commit tests (NFC)
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‎llvm/test/Transforms/InstCombine/ashr-lshr.ll

Lines changed: 259 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -604,3 +604,262 @@ define <2 x i8> @ashr_known_pos_exact_vec(<2 x i8> %x, <2 x i8> %y) {
604604
%r = ashr exact <2 x i8> %p, %y
605605
ret <2 x i8> %r
606606
}
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define i32 @lshr_mul_times_3_div_2(i32 %0) {
609+
; CHECK-LABEL: @lshr_mul_times_3_div_2(
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; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 3
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 1
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; CHECK-NEXT: ret i32 [[LSHR]]
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;
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%mul = mul nsw nuw i32 %0, 3
615+
%lshr = lshr i32 %mul, 1
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ret i32 %lshr
617+
}
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619+
define i32 @lshr_mul_times_3_div_2_exact(i32 %x) {
620+
; CHECK-LABEL: @lshr_mul_times_3_div_2_exact(
621+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 3
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; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[MUL]], 1
623+
; CHECK-NEXT: ret i32 [[LSHR]]
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;
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%mul = mul nsw i32 %x, 3
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%lshr = lshr exact i32 %mul, 1
627+
ret i32 %lshr
628+
}
629+
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; Negative test
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define i32 @lshr_mul_times_3_div_2_no_flags(i32 %0) {
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; CHECK-LABEL: @lshr_mul_times_3_div_2_no_flags(
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[TMP0:%.*]], 3
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 1
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; CHECK-NEXT: ret i32 [[LSHR]]
637+
;
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%mul = mul i32 %0, 3
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%lshr = lshr i32 %mul, 1
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ret i32 %lshr
641+
}
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; Negative test
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define i32 @mul_times_3_div_2_multiuse_lshr(i32 %x) {
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; CHECK-LABEL: @mul_times_3_div_2_multiuse_lshr(
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; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
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; CHECK-NEXT: [[RES:%.*]] = lshr i32 [[MUL]], 1
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; CHECK-NEXT: call void @use(i32 [[MUL]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%mul = mul nuw i32 %x, 3
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%res = lshr i32 %mul, 1
654+
call void @use(i32 %mul)
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ret i32 %res
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}
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define i32 @lshr_mul_times_3_div_2_exact_2(i32 %x) {
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; CHECK-LABEL: @lshr_mul_times_3_div_2_exact_2(
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; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
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; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[MUL]], 1
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; CHECK-NEXT: ret i32 [[LSHR]]
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;
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%mul = mul nuw i32 %x, 3
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%lshr = lshr exact i32 %mul, 1
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ret i32 %lshr
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}
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define i32 @lshr_mul_times_5_div_4(i32 %0) {
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; CHECK-LABEL: @lshr_mul_times_5_div_4(
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; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 5
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 2
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; CHECK-NEXT: ret i32 [[LSHR]]
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;
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%mul = mul nsw nuw i32 %0, 5
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%lshr = lshr i32 %mul, 2
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ret i32 %lshr
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}
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define i32 @lshr_mul_times_5_div_4_exact(i32 %x) {
681+
; CHECK-LABEL: @lshr_mul_times_5_div_4_exact(
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 5
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; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[MUL]], 2
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; CHECK-NEXT: ret i32 [[LSHR]]
685+
;
686+
%mul = mul nsw i32 %x, 5
687+
%lshr = lshr exact i32 %mul, 2
688+
ret i32 %lshr
689+
}
690+
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; Negative test
692+
693+
define i32 @lshr_mul_times_5_div_4_no_flags(i32 %0) {
694+
; CHECK-LABEL: @lshr_mul_times_5_div_4_no_flags(
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[TMP0:%.*]], 5
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 2
697+
; CHECK-NEXT: ret i32 [[LSHR]]
698+
;
699+
%mul = mul i32 %0, 5
700+
%lshr = lshr i32 %mul, 2
701+
ret i32 %lshr
702+
}
703+
704+
; Negative test
705+
706+
define i32 @mul_times_5_div_4_multiuse_lshr(i32 %x) {
707+
; CHECK-LABEL: @mul_times_5_div_4_multiuse_lshr(
708+
; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 5
709+
; CHECK-NEXT: [[RES:%.*]] = lshr i32 [[MUL]], 2
710+
; CHECK-NEXT: call void @use(i32 [[MUL]])
711+
; CHECK-NEXT: ret i32 [[RES]]
712+
;
713+
%mul = mul nuw i32 %x, 5
714+
%res = lshr i32 %mul, 2
715+
call void @use(i32 %mul)
716+
ret i32 %res
717+
}
718+
719+
define i32 @lshr_mul_times_5_div_4_exact_2(i32 %x) {
720+
; CHECK-LABEL: @lshr_mul_times_5_div_4_exact_2(
721+
; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 5
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; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[MUL]], 2
723+
; CHECK-NEXT: ret i32 [[LSHR]]
724+
;
725+
%mul = mul nuw i32 %x, 5
726+
%lshr = lshr exact i32 %mul, 2
727+
ret i32 %lshr
728+
}
729+
730+
define i32 @ashr_mul_times_3_div_2(i32 %0) {
731+
; CHECK-LABEL: @ashr_mul_times_3_div_2(
732+
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 3
733+
; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[MUL]], 1
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; CHECK-NEXT: ret i32 [[ASHR]]
735+
;
736+
%mul = mul nuw nsw i32 %0, 3
737+
%ashr = ashr i32 %mul, 1
738+
ret i32 %ashr
739+
}
740+
741+
define i32 @ashr_mul_times_3_div_2_exact(i32 %x) {
742+
; CHECK-LABEL: @ashr_mul_times_3_div_2_exact(
743+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 3
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; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 1
745+
; CHECK-NEXT: ret i32 [[ASHR]]
746+
;
747+
%mul = mul nsw i32 %x, 3
748+
%ashr = ashr exact i32 %mul, 1
749+
ret i32 %ashr
750+
}
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752+
; Negative test
753+
754+
define i32 @ashr_mul_times_3_div_2_no_flags(i32 %0) {
755+
; CHECK-LABEL: @ashr_mul_times_3_div_2_no_flags(
756+
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[TMP0:%.*]], 3
757+
; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[MUL]], 1
758+
; CHECK-NEXT: ret i32 [[ASHR]]
759+
;
760+
%mul = mul i32 %0, 3
761+
%ashr = ashr i32 %mul, 1
762+
ret i32 %ashr
763+
}
764+
765+
; Negative test
766+
767+
define i32 @ashr_mul_times_3_div_2_no_nsw(i32 %0) {
768+
; CHECK-LABEL: @ashr_mul_times_3_div_2_no_nsw(
769+
; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[TMP0:%.*]], 3
770+
; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[MUL]], 1
771+
; CHECK-NEXT: ret i32 [[ASHR]]
772+
;
773+
%mul = mul nuw i32 %0, 3
774+
%ashr = ashr i32 %mul, 1
775+
ret i32 %ashr
776+
}
777+
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; Negative test
779+
780+
define i32 @mul_times_3_div_2_multiuse_ashr(i32 %x) {
781+
; CHECK-LABEL: @mul_times_3_div_2_multiuse_ashr(
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 3
783+
; CHECK-NEXT: [[RES:%.*]] = ashr i32 [[MUL]], 1
784+
; CHECK-NEXT: call void @use(i32 [[MUL]])
785+
; CHECK-NEXT: ret i32 [[RES]]
786+
;
787+
%mul = mul nsw i32 %x, 3
788+
%res = ashr i32 %mul, 1
789+
call void @use(i32 %mul)
790+
ret i32 %res
791+
}
792+
793+
define i32 @ashr_mul_times_3_div_2_exact_2(i32 %x) {
794+
; CHECK-LABEL: @ashr_mul_times_3_div_2_exact_2(
795+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 3
796+
; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 1
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; CHECK-NEXT: ret i32 [[ASHR]]
798+
;
799+
%mul = mul nsw i32 %x, 3
800+
%ashr = ashr exact i32 %mul, 1
801+
ret i32 %ashr
802+
}
803+
804+
define i32 @ashr_mul_times_5_div_4(i32 %0) {
805+
; CHECK-LABEL: @ashr_mul_times_5_div_4(
806+
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 5
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; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[MUL]], 2
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; CHECK-NEXT: ret i32 [[ASHR]]
809+
;
810+
%mul = mul nuw nsw i32 %0, 5
811+
%ashr = ashr i32 %mul, 2
812+
ret i32 %ashr
813+
}
814+
815+
define i32 @ashr_mul_times_5_div_4_exact(i32 %x) {
816+
; CHECK-LABEL: @ashr_mul_times_5_div_4_exact(
817+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 5
818+
; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 2
819+
; CHECK-NEXT: ret i32 [[ASHR]]
820+
;
821+
%mul = mul nsw i32 %x, 5
822+
%ashr = ashr exact i32 %mul, 2
823+
ret i32 %ashr
824+
}
825+
826+
; Negative test
827+
828+
define i32 @ashr_mul_times_5_div_4_no_flags(i32 %0) {
829+
; CHECK-LABEL: @ashr_mul_times_5_div_4_no_flags(
830+
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[TMP0:%.*]], 5
831+
; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[MUL]], 2
832+
; CHECK-NEXT: ret i32 [[ASHR]]
833+
;
834+
%mul = mul i32 %0, 5
835+
%ashr = ashr i32 %mul, 2
836+
ret i32 %ashr
837+
}
838+
839+
; Negative test
840+
841+
define i32 @mul_times_5_div_4_multiuse_ashr(i32 %x) {
842+
; CHECK-LABEL: @mul_times_5_div_4_multiuse_ashr(
843+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 5
844+
; CHECK-NEXT: [[RES:%.*]] = ashr i32 [[MUL]], 2
845+
; CHECK-NEXT: call void @use(i32 [[MUL]])
846+
; CHECK-NEXT: ret i32 [[RES]]
847+
;
848+
%mul = mul nsw i32 %x, 5
849+
%res = ashr i32 %mul, 2
850+
call void @use(i32 %mul)
851+
ret i32 %res
852+
}
853+
854+
define i32 @ashr_mul_times_5_div_4_exact_2(i32 %x) {
855+
; CHECK-LABEL: @ashr_mul_times_5_div_4_exact_2(
856+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 5
857+
; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 2
858+
; CHECK-NEXT: ret i32 [[ASHR]]
859+
;
860+
%mul = mul nsw i32 %x, 5
861+
%ashr = ashr exact i32 %mul, 2
862+
ret i32 %ashr
863+
}
864+
865+
declare void @use(i32)

‎llvm/test/Transforms/InstCombine/lshr.ll

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -628,7 +628,7 @@ define i32 @mul_splat_fold_wrong_lshr_const(i32 %x) {
628628
ret i32 %t
629629
}
630630

631-
; Negative test
631+
; Negative test (but simplifies into a different transform)
632632

633633
define i32 @mul_splat_fold_no_nuw(i32 %x) {
634634
; CHECK-LABEL: @mul_splat_fold_no_nuw(
@@ -641,6 +641,19 @@ define i32 @mul_splat_fold_no_nuw(i32 %x) {
641641
ret i32 %t
642642
}
643643

644+
; Negative test
645+
646+
define i32 @mul_splat_fold_no_flags(i32 %x) {
647+
; CHECK-LABEL: @mul_splat_fold_no_flags(
648+
; CHECK-NEXT: [[M:%.*]] = mul i32 [[X:%.*]], 65537
649+
; CHECK-NEXT: [[T:%.*]] = lshr i32 [[M]], 16
650+
; CHECK-NEXT: ret i32 [[T]]
651+
;
652+
%m = mul i32 %x, 65537
653+
%t = lshr i32 %m, 16
654+
ret i32 %t
655+
}
656+
644657
; Negative test (but simplifies before we reach the mul_splat transform)- need more than 2 bits
645658

646659
define i2 @mul_splat_fold_too_narrow(i2 %x) {

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