@@ -2769,12 +2769,15 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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// available.
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if (!TmpReg)
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TmpReg = RS->scavengeRegisterBackwards (AMDGPU::SReg_32_XM0RegClass,
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- MI, false , 0 );
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- BuildMI (*MBB, *MI, DL, TII->get (AMDGPU::S_LSHR_B32))
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- .addDef (TmpReg, RegState::Renamable)
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- .addReg (FrameReg)
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- .addImm (ST.getWavefrontSizeLog2 ())
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- .setOperandDead (3 ); // Set SCC dead
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+ MI, /* RestoreAfter=*/ false , 0 ,
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+ /* AllowSpill=*/ false );
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+ if (TmpReg) {
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+ BuildMI (*MBB, *MI, DL, TII->get (AMDGPU::S_LSHR_B32))
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+ .addDef (TmpReg, RegState::Renamable)
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+ .addReg (FrameReg)
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+ .addImm (ST.getWavefrontSizeLog2 ())
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+ .setOperandDead (3 ); // Set SCC dead
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+ }
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MaterializedReg = TmpReg;
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}
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@@ -2802,18 +2805,20 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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DstReg = TmpReg;
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}
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- auto AddI32 = BuildMI (*MBB, *MI, DL, MI->getDesc ())
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- .addDef (DstReg, RegState::Renamable)
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- .addReg (MaterializedReg, RegState::Kill)
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- .add (OtherOp);
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- if (DeadSCC)
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- AddI32.setOperandDead (3 );
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+ if (TmpReg) {
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+ auto AddI32 = BuildMI (*MBB, *MI, DL, MI->getDesc ())
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+ .addDef (DstReg, RegState::Renamable)
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+ .addReg (MaterializedReg, RegState::Kill)
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+ .add (OtherOp);
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+ if (DeadSCC)
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+ AddI32.setOperandDead (3 );
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- MaterializedReg = DstReg;
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+ MaterializedReg = DstReg;
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- OtherOp.ChangeToRegister (MaterializedReg, false );
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- OtherOp.setIsKill (true );
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- OtherOp.setIsRenamable (true );
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+ OtherOp.ChangeToRegister (MaterializedReg, false );
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+ OtherOp.setIsKill (true );
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+ OtherOp.setIsRenamable (true );
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+ }
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FIOp->ChangeToImmediate (Offset);
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} else {
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// If we don't have any other offset to apply, we can just directly
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