[RISCV] Kill off redundant field XLenVT [nfc]

We're already tracking XLen, we can compute XLenVt from that.  Note that XLen itself should probably be driven from IsRV64 (the processor flag), but I'm leaving that to a separate change (with review).

Author: preames

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

@@ -66,10 +66,8 @@ RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
     TuneCPU = CPU;
 
   ParseSubtargetFeatures(CPU, TuneCPU, FS);
-  if (Is64Bit) {
-    XLenVT = MVT::i64;
+  if (Is64Bit)
     XLen = 64;
-  }
 
   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
   RISCVFeatures::validate(TT, getFeatureBits());

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -50,7 +50,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
 
   unsigned XLen = 32;
   unsigned ZvlLen = 0;
-  MVT XLenVT = MVT::i32;
   unsigned RVVVectorBitsMin;
   unsigned RVVVectorBitsMax;
   uint8_t MaxInterleaveFactor = 2;
@@ -127,8 +126,14 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     return hasStdExtZfhOrZfhmin() || HasStdExtZfbfmin;
   }
   bool is64Bit() const { return IsRV64; }
-  MVT getXLenVT() const { return XLenVT; }
-  unsigned getXLen() const { return XLen; }
+  MVT getXLenVT() const {
+    return MVT::getIntegerVT(getXLen());
+  }
+  unsigned getXLen() const {
+    assert((XLen == 32 || XLen == 64) &&
+           "unexpected xlen");
+    return XLen;
+  }
   unsigned getFLen() const {
     if (HasStdExtD)
       return 64;