@@ -1432,6 +1432,140 @@ define <2 x i8> @sdiv_sdiv_mul_nsw(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
1432
1432
ret <2 x i8 > %r
1433
1433
}
1434
1434
1435
+ ; (X * C0) / (X * C1) --> C0 / C1
1436
+ define i8 @sdiv_mul_nsw_mul_nsw (i8 %x ,i8 %y ,i8 %z ) {
1437
+ ; CHECK-LABEL: @sdiv_mul_nsw_mul_nsw(
1438
+ ; CHECK-NEXT: [[ADD4:%.*]] = mul nsw i8 [[X:%.*]], [[Z:%.*]]
1439
+ ; CHECK-NEXT: [[ADD5:%.*]] = mul nsw i8 [[X]], [[Y:%.*]]
1440
+ ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[ADD5]], [[ADD4]]
1441
+ ; CHECK-NEXT: ret i8 [[DIV]]
1442
+ ;
1443
+ %add4 = mul nsw i8 %x , %z
1444
+ %add5 = mul nsw i8 %x , %y
1445
+ %div = sdiv i8 %add5 , %add4
1446
+ ret i8 %div
1447
+ }
1448
+
1449
+ define i8 @udiv_mul_nuw_mul_nuw (i8 %x ,i8 %y ,i8 %z ) {
1450
+ ; CHECK-LABEL: @udiv_mul_nuw_mul_nuw(
1451
+ ; CHECK-NEXT: [[DIV:%.*]] = udiv i8 [[Y:%.*]], [[Z:%.*]]
1452
+ ; CHECK-NEXT: ret i8 [[DIV]]
1453
+ ;
1454
+ %add4 = mul nuw i8 %x , %z
1455
+ %add5 = mul nuw i8 %x , %y
1456
+ %div = udiv i8 %add5 , %add4
1457
+ ret i8 %div
1458
+ }
1459
+
1460
+ define i8 @sdiv_mul_nsw_constant_mul_nsw_constant (i8 %x ) {
1461
+ ; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_nsw_constant(
1462
+ ; CHECK-NEXT: ret i8 2
1463
+ ;
1464
+ %add4 = mul nsw i8 %x , 5
1465
+ %add5 = mul nsw i8 %x , 10
1466
+ %div = sdiv i8 %add5 , %add4
1467
+ ret i8 %div
1468
+ }
1469
+
1470
+ define i4 @sdiv_mul_nsw_constant_mul_constant (i4 %a ) {
1471
+ ; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_constant(
1472
+ ; CHECK-NEXT: [[ADD4:%.*]] = mul i4 [[A:%.*]], 3
1473
+ ; CHECK-NEXT: [[ADD5:%.*]] = mul nsw i4 [[A]], 6
1474
+ ; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]]
1475
+ ; CHECK-NEXT: ret i4 [[DIV]]
1476
+ ;
1477
+ %add4 = mul i4 %a , 3
1478
+ %add5 = mul nsw i4 %a , 6
1479
+ %div = sdiv i4 %add5 , %add4
1480
+ ret i4 %div
1481
+ }
1482
+ define i4 @sdiv_mul_nsw_constant_mul_constant2 (i4 %a ) {
1483
+ ; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_constant2(
1484
+ ; CHECK-NEXT: [[ADD4:%.*]] = sub i4 0, [[A:%.*]]
1485
+ ; CHECK-NEXT: [[ADD5:%.*]] = shl i4 [[A]], 3
1486
+ ; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]]
1487
+ ; CHECK-NEXT: ret i4 [[DIV]]
1488
+ ;
1489
+ %add4 = mul i4 %a , 15
1490
+ %add5 = mul nsw i4 %a , 8
1491
+ %div = sdiv i4 %add5 , %add4
1492
+ ret i4 %div
1493
+ }
1494
+
1495
+ define i4 @sdiv_mul_nsw_constant_mul_constant3 (i4 %a ) {
1496
+ ; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_constant3(
1497
+ ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i4 [[A:%.*]], -8
1498
+ ; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], i4 1, i4 -1
1499
+ ; CHECK-NEXT: ret i4 [[DIV]]
1500
+ ;
1501
+ %add4 = mul i4 %a , 15
1502
+ %add5 = mul nsw i4 %a , 1
1503
+ %div = sdiv i4 %add5 , %add4
1504
+ ret i4 %div
1505
+ }
1506
+
1507
+ define i4 @sdiv_mul_nsw_mul (i4 %a ) {
1508
+ ; CHECK-LABEL: @sdiv_mul_nsw_mul(
1509
+ ; CHECK-NEXT: [[ADD4:%.*]] = sub i4 0, [[A:%.*]]
1510
+ ; CHECK-NEXT: [[ADD5:%.*]] = shl i4 [[A]], 3
1511
+ ; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]]
1512
+ ; CHECK-NEXT: ret i4 [[DIV]]
1513
+ ;
1514
+ %add4 = mul i4 %a , -1
1515
+ %add5 = mul nsw i4 %a , -8
1516
+ %div = sdiv i4 %add5 , %add4
1517
+ ret i4 %div
1518
+ }
1519
+
1520
+ define i4 @udiv_mul_nuw_constant_mul_constant (i4 %a ) {
1521
+ ; CHECK-LABEL: @udiv_mul_nuw_constant_mul_constant(
1522
+ ; CHECK-NEXT: ret i4 2
1523
+ ;
1524
+ %add4 = mul i4 %a , 3
1525
+ %add5 = mul nuw i4 %a , 6
1526
+ %div = udiv i4 %add5 , %add4
1527
+ ret i4 %div
1528
+ }
1529
+
1530
+ define i4 @udiv_mul_nuw_mul_negative (i4 %a ) {
1531
+ ; CHECK-LABEL: @udiv_mul_nuw_mul_negative(
1532
+ ; CHECK-NEXT: [[ADD4:%.*]] = mul i4 [[A:%.*]], -3
1533
+ ; CHECK-NEXT: [[ADD5:%.*]] = shl nuw i4 [[A]], 2
1534
+ ; CHECK-NEXT: [[DIV:%.*]] = udiv i4 [[ADD5]], [[ADD4]]
1535
+ ; CHECK-NEXT: ret i4 [[DIV]]
1536
+ ;
1537
+ %add4 = mul i4 %a , 13
1538
+ %add5 = mul nuw i4 %a , 4
1539
+ %div = udiv i4 %add5 , %add4
1540
+ ret i4 %div
1541
+ }
1542
+
1543
+ define i4 @sdiv_mul_nsw_mul_nsw_allones (i4 %a ) {
1544
+ ; CHECK-LABEL: @sdiv_mul_nsw_mul_nsw_allones(
1545
+ ; CHECK-NEXT: [[ADD4:%.*]] = sub nsw i4 0, [[A:%.*]]
1546
+ ; CHECK-NEXT: [[ADD5:%.*]] = shl i4 [[A]], 3
1547
+ ; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]]
1548
+ ; CHECK-NEXT: ret i4 [[DIV]]
1549
+ ;
1550
+ %add4 = mul nsw i4 %a , -1
1551
+ %add5 = mul nsw i4 %a , -8
1552
+ %div = sdiv i4 %add5 , %add4
1553
+ ret i4 %div
1554
+ }
1555
+
1556
+ define i4 @sdiv_mul_nsw_mul_signmask (i4 %a , i4 %c2 ) {
1557
+ ; CHECK-LABEL: @sdiv_mul_nsw_mul_signmask(
1558
+ ; CHECK-NEXT: [[ADD4:%.*]] = shl i4 [[A:%.*]], 3
1559
+ ; CHECK-NEXT: [[ADD5:%.*]] = mul nsw i4 [[A]], [[C2:%.*]]
1560
+ ; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]]
1561
+ ; CHECK-NEXT: ret i4 [[DIV]]
1562
+ ;
1563
+ %add4 = mul nsw i4 %a , -8
1564
+ %add5 = mul nsw i4 %a , %c2
1565
+ %div = sdiv i4 %add5 , %add4
1566
+ ret i4 %div
1567
+ }
1568
+
1435
1569
define i32 @sdiv_sub1 (i32 %arg ) {
1436
1570
; CHECK-LABEL: @sdiv_sub1(
1437
1571
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[ARG:%.*]], -2147483648
0 commit comments