Skip to content

Commit 1c55b22

Browse files
authored
[AMDGPU] Add GFX12 encoding and aliases for existing SOP (SALU) instructions (#74305)
1 parent fd870c6 commit 1c55b22

15 files changed

+25454
-268
lines changed

llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1460,6 +1460,8 @@ def FeatureISAVersion12 : FeatureSet<
14601460
FeatureExtendedImageInsts,
14611461
FeaturePackedTID,
14621462
FeatureVcmpxPermlaneHazard,
1463+
FeatureSALUFloatInsts,
1464+
FeatureVGPRSingleUseHintInsts,
14631465
FeatureMADIntraFwdBug]>;
14641466

14651467
//===----------------------------------------------------------------------===//

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -610,6 +610,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
610610
Address, CS);
611611
if (Res) break;
612612

613+
Res = tryDecodeInst(DecoderTableGFX1232, MI, DW, Address, CS);
614+
if (Res)
615+
break;
616+
613617
if (Bytes.size() < 4) break;
614618
const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
615619

@@ -637,6 +641,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
637641
Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS);
638642
if (Res) break;
639643

644+
Res = tryDecodeInst(DecoderTableGFX1264, MI, QW, Address, CS);
645+
if (Res)
646+
break;
647+
640648
Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
641649
Address, CS);
642650
if (Res)

llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 428 additions & 268 deletions
Large diffs are not rendered by default.

0 commit comments

Comments
 (0)