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[SCEV] Add tests where one wrap predicate implies another.
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‎llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll

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; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes='print<access-info>' %s -disable-output 2>&1 | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
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; FIXME: {0,+,3} implies {0,+,2}.
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define void @wrap_check_iv.3_implies_iv.2(i32 noundef %N, ptr %dst, ptr %src) {
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; CHECK-LABEL: 'wrap_check_iv.3_implies_iv.2'
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; CHECK-NEXT: loop:
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; CHECK-NEXT: Memory dependences are safe with run-time checks
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; CHECK-NEXT: Dependences:
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; CHECK-NEXT: Run-time memory checks:
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; CHECK-NEXT: Check 0:
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; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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; CHECK-NEXT: Grouped accesses:
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; CHECK-NEXT: Group [[GRP1]]:
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; CHECK-NEXT: (Low: %dst High: (4 + (12 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %dst))
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; CHECK-NEXT: Member: {%dst,+,12}<%loop>
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; CHECK-NEXT: Group [[GRP2]]:
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; CHECK-NEXT: (Low: %src High: (4 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %src))
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; CHECK-NEXT: Member: {%src,+,8}<%loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
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; CHECK-NEXT: SCEV assumptions:
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; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nssw>
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; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
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; CHECK-EMPTY:
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; CHECK-NEXT: Expressions re-written:
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; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,2}<%loop> to i64))<nsw> + %src)
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; CHECK-NEXT: --> {%src,+,8}<%loop>
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; CHECK-NEXT: [PSE] %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,3}<%loop> to i64))<nsw> + %dst)
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; CHECK-NEXT: --> {%dst,+,12}<%loop>
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;
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entry:
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br label %loop
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loop:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ]
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%iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]
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%iv.3 = phi i32 [ 0, %entry ], [ %iv.3.next, %loop ]
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%ext.iv.2 = sext i32 %iv.2 to i64
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%gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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%l = load i32, ptr %gep.iv.2, align 4
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%ext.iv.3 = sext i32 %iv.3 to i64
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%gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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store i32 %l, ptr %gep.iv.3, align 4
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%iv.1.next = add nuw nsw i32 %iv.1, 1
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%iv.2.next = add i32 %iv.2, 2
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%iv.3.next = add i32 %iv.3, 3
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%ec = icmp eq i32 %iv.1.next, %N
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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; FIXME: {2,+,2} implies {0,+,2}.
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define void @wrap_check_iv.3_implies_iv.2_different_start(i32 noundef %N, ptr %dst, ptr %src) {
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; CHECK-LABEL: 'wrap_check_iv.3_implies_iv.2_different_start'
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; CHECK-NEXT: loop:
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; CHECK-NEXT: Memory dependences are safe with run-time checks
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; CHECK-NEXT: Dependences:
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; CHECK-NEXT: Run-time memory checks:
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; CHECK-NEXT: Check 0:
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; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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; CHECK-NEXT: Grouped accesses:
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; CHECK-NEXT: Group [[GRP3]]:
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; CHECK-NEXT: (Low: (12 + %dst) High: (16 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %dst))
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; CHECK-NEXT: Member: {(12 + %dst),+,8}<%loop>
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; CHECK-NEXT: Group [[GRP4]]:
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; CHECK-NEXT: (Low: %src High: (4 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %src))
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; CHECK-NEXT: Member: {%src,+,8}<%loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
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; CHECK-NEXT: SCEV assumptions:
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; CHECK-NEXT: {2,+,2}<%loop> Added Flags: <nssw>
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; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
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; CHECK-EMPTY:
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; CHECK-NEXT: Expressions re-written:
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; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,2}<%loop> to i64))<nsw> + %src)
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; CHECK-NEXT: --> {%src,+,8}<%loop>
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; CHECK-NEXT: [PSE] %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3:
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; CHECK-NEXT: (4 + (4 * (sext i32 {2,+,2}<%loop> to i64))<nsw> + %dst)
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; CHECK-NEXT: --> {(12 + %dst),+,8}<%loop>
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;
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entry:
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br label %loop
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loop:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ]
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%iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]
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%iv.3 = phi i32 [ 3, %entry ], [ %iv.3.next, %loop ]
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%ext.iv.2 = sext i32 %iv.2 to i64
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%gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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%l = load i32, ptr %gep.iv.2, align 4
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%ext.iv.3 = sext i32 %iv.3 to i64
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%gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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store i32 %l, ptr %gep.iv.3, align 4
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%iv.1.next = add nuw nsw i32 %iv.1, 1
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%iv.2.next = add i32 %iv.2, 2
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%iv.3.next = add i32 %iv.3, 2
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%ec = icmp eq i32 %iv.1.next, %N
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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; FIXME: {0,+,3} implies {0,+,2}.
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define void @wrap_check_iv.3_implies_iv.2_predicates_added_in_different_order(i32 noundef %N, ptr %dst, ptr %src) {
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; CHECK-LABEL: 'wrap_check_iv.3_implies_iv.2_predicates_added_in_different_order'
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; CHECK-NEXT: loop:
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; CHECK-NEXT: Memory dependences are safe with run-time checks
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; CHECK-NEXT: Dependences:
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; CHECK-NEXT: Run-time memory checks:
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; CHECK-NEXT: Check 0:
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; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.2 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.2
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; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.3 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.3
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; CHECK-NEXT: Grouped accesses:
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; CHECK-NEXT: Group [[GRP5]]:
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; CHECK-NEXT: (Low: %dst High: (4 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %dst))
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; CHECK-NEXT: Member: {%dst,+,8}<%loop>
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; CHECK-NEXT: Group [[GRP6]]:
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; CHECK-NEXT: (Low: %src High: (4 + (12 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %src))
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; CHECK-NEXT: Member: {%src,+,12}<%loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
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; CHECK-NEXT: SCEV assumptions:
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; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
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; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nssw>
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; CHECK-EMPTY:
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; CHECK-NEXT: Expressions re-written:
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; CHECK-NEXT: [PSE] %gep.iv.3 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.3:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,3}<%loop> to i64))<nsw> + %src)
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; CHECK-NEXT: --> {%src,+,12}<%loop>
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; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.2:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,2}<%loop> to i64))<nsw> + %dst)
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; CHECK-NEXT: --> {%dst,+,8}<%loop>
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;
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entry:
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br label %loop
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loop:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ]
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%iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]
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%iv.3 = phi i32 [ 0, %entry ], [ %iv.3.next, %loop ]
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%ext.iv.3 = sext i32 %iv.3 to i64
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%gep.iv.3 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.3
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%l = load i32, ptr %gep.iv.3, align 4
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%ext.iv.2 = sext i32 %iv.2 to i64
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%gep.iv.2 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.2
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store i32 %l, ptr %gep.iv.2, align 4
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%iv.1.next = add nuw nsw i32 %iv.1, 1
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%iv.2.next = add i32 %iv.2, 2
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%iv.3.next = add i32 %iv.3, 3
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%ec = icmp eq i32 %iv.1.next, %N
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @wrap_check_iv.3_does_not_implies_iv.2_due_to_start(i32 noundef %N, ptr %dst, ptr %src) {
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; CHECK-LABEL: 'wrap_check_iv.3_does_not_implies_iv.2_due_to_start'
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; CHECK-NEXT: loop:
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; CHECK-NEXT: Memory dependences are safe with run-time checks
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; CHECK-NEXT: Dependences:
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; CHECK-NEXT: Run-time memory checks:
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; CHECK-NEXT: Check 0:
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; CHECK-NEXT: Comparing group ([[GRP7:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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; CHECK-NEXT: Against group ([[GRP8:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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; CHECK-NEXT: Grouped accesses:
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; CHECK-NEXT: Group [[GRP7]]:
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; CHECK-NEXT: (Low: %dst High: (4 + (12 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %dst))
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; CHECK-NEXT: Member: {%dst,+,12}<%loop>
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; CHECK-NEXT: Group [[GRP8]]:
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; CHECK-NEXT: (Low: (40 + %src) High: (44 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %src))
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; CHECK-NEXT: Member: {(40 + %src),+,8}<%loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
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; CHECK-NEXT: SCEV assumptions:
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; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nssw>
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; CHECK-NEXT: {10,+,2}<%loop> Added Flags: <nssw>
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; CHECK-EMPTY:
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; CHECK-NEXT: Expressions re-written:
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; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
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; CHECK-NEXT: ((4 * (sext i32 {10,+,2}<%loop> to i64))<nsw> + %src)
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; CHECK-NEXT: --> {(40 + %src),+,8}<%loop>
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; CHECK-NEXT: [PSE] %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,3}<%loop> to i64))<nsw> + %dst)
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; CHECK-NEXT: --> {%dst,+,12}<%loop>
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;
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entry:
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br label %loop
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loop:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ]
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%iv.2 = phi i32 [ 10, %entry ], [ %iv.2.next, %loop ]
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%iv.3 = phi i32 [ 0, %entry ], [ %iv.3.next, %loop ]
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%ext.iv.2 = sext i32 %iv.2 to i64
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%gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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%l = load i32, ptr %gep.iv.2, align 4
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%ext.iv.3 = sext i32 %iv.3 to i64
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%gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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store i32 %l, ptr %gep.iv.3, align 4
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%iv.1.next = add nuw nsw i32 %iv.1, 1
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%iv.2.next = add i32 %iv.2, 2
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%iv.3.next = add i32 %iv.3, 3
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%ec = icmp eq i32 %iv.1.next, %N
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @wrap_check_iv.3_does_not_imply_iv.2_due_to_start_negative(i32 noundef %N, ptr %dst, ptr %src) {
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; CHECK-LABEL: 'wrap_check_iv.3_does_not_imply_iv.2_due_to_start_negative'
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; CHECK-NEXT: loop:
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; CHECK-NEXT: Memory dependences are safe with run-time checks
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; CHECK-NEXT: Dependences:
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; CHECK-NEXT: Run-time memory checks:
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; CHECK-NEXT: Check 0:
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; CHECK-NEXT: Comparing group ([[GRP9:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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; CHECK-NEXT: Against group ([[GRP10:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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; CHECK-NEXT: Grouped accesses:
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; CHECK-NEXT: Group [[GRP9]]:
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; CHECK-NEXT: (Low: (-4 + %dst) High: ((12 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %dst))
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; CHECK-NEXT: Member: {(-4 + %dst),+,12}<%loop>
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; CHECK-NEXT: Group [[GRP10]]:
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; CHECK-NEXT: (Low: %src High: (4 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %src))
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; CHECK-NEXT: Member: {%src,+,8}<%loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
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; CHECK-NEXT: SCEV assumptions:
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; CHECK-NEXT: {-1,+,3}<%loop> Added Flags: <nssw>
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; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
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; CHECK-EMPTY:
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; CHECK-NEXT: Expressions re-written:
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; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,2}<%loop> to i64))<nsw> + %src)
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; CHECK-NEXT: --> {%src,+,8}<%loop>
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; CHECK-NEXT: [PSE] %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3:
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; CHECK-NEXT: ((4 * (sext i32 {-1,+,3}<%loop> to i64))<nsw> + %dst)
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; CHECK-NEXT: --> {(-4 + %dst),+,12}<%loop>
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;
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entry:
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br label %loop
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loop:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ]
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%iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]
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%iv.3 = phi i32 [ -1, %entry ], [ %iv.3.next, %loop ]
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%ext.iv.2 = sext i32 %iv.2 to i64
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%gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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%l = load i32, ptr %gep.iv.2, align 4
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%ext.iv.3 = sext i32 %iv.3 to i64
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%gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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store i32 %l, ptr %gep.iv.3, align 4
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%iv.1.next = add nuw nsw i32 %iv.1, 1
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%iv.2.next = add i32 %iv.2, 2
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%iv.3.next = add i32 %iv.3, 3
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%ec = icmp eq i32 %iv.1.next, %N
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @wrap_check_iv.3_does_not_imply_iv.2_due_to_negative_step(i32 noundef %N, ptr %dst, ptr %src) {
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; CHECK-LABEL: 'wrap_check_iv.3_does_not_imply_iv.2_due_to_negative_step'
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; CHECK-NEXT: loop:
287+
; CHECK-NEXT: Memory dependences are safe with run-time checks
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; CHECK-NEXT: Dependences:
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; CHECK-NEXT: Run-time memory checks:
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; CHECK-NEXT: Check 0:
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; CHECK-NEXT: Comparing group ([[GRP11:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
293+
; CHECK-NEXT: Against group ([[GRP12:0x[0-9a-f]+]]):
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; CHECK-NEXT: %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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; CHECK-NEXT: Grouped accesses:
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; CHECK-NEXT: Group [[GRP11]]:
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; CHECK-NEXT: (Low: ((-4 * (zext i32 (-1 + %N) to i64))<nsw> + %dst) High: (4 + %dst))
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; CHECK-NEXT: Member: {%dst,+,-4}<%loop>
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; CHECK-NEXT: Group [[GRP12]]:
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; CHECK-NEXT: (Low: %src High: (4 + (8 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %src))
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; CHECK-NEXT: Member: {%src,+,8}<%loop>
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; CHECK-EMPTY:
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; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
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; CHECK-NEXT: SCEV assumptions:
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; CHECK-NEXT: {0,+,-1}<%loop> Added Flags: <nssw>
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; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
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; CHECK-EMPTY:
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; CHECK-NEXT: Expressions re-written:
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; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,2}<%loop> to i64))<nsw> + %src)
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; CHECK-NEXT: --> {%src,+,8}<%loop>
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; CHECK-NEXT: [PSE] %gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3:
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; CHECK-NEXT: ((4 * (sext i32 {0,+,-1}<%loop> to i64))<nsw> + %dst)
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; CHECK-NEXT: --> {%dst,+,-4}<%loop>
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;
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entry:
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br label %loop
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loop:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ]
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%iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]
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%iv.3 = phi i32 [ 0, %entry ], [ %iv.3.next, %loop ]
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%ext.iv.2 = sext i32 %iv.2 to i64
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%gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2
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%l = load i32, ptr %gep.iv.2, align 4
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%ext.iv.3 = sext i32 %iv.3 to i64
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%gep.iv.3 = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.3
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store i32 %l, ptr %gep.iv.3, align 4
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%iv.1.next = add nuw nsw i32 %iv.1, 1
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%iv.2.next = add i32 %iv.2, 2
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%iv.3.next = add i32 %iv.3, -1
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%ec = icmp eq i32 %iv.1.next, %N
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}

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