Skip to content

Commit 1cdf85f

Browse files
committed
Rebase to use the new search tables
1 parent 3b00b13 commit 1cdf85f

File tree

1 file changed

+11
-17
lines changed

1 file changed

+11
-17
lines changed

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

Lines changed: 11 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121

2222
#define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"
2323

24-
namespace llvm::RISCV::mca {
24+
namespace llvm::RISCV {
2525
struct VXMemOpInfo {
2626
unsigned Log2IdxEEW : 3;
2727
unsigned IsOrdered : 1;
@@ -31,14 +31,8 @@ struct VXMemOpInfo {
3131
};
3232

3333
#define GET_RISCVBaseVXMemOpTable_IMPL
34-
// We need to include the implementation code here because RISCVCustomBehavior
35-
// is not linked against RISCVCodeGen.
36-
#define GET_RISCVVLXSEGTable_IMPL
37-
#define GET_RISCVVSXSEGTable_IMPL
38-
#define GET_RISCVVLXTable_IMPL
39-
#define GET_RISCVVSXTable_IMPL
4034
#include "RISCVGenSearchableTables.inc"
41-
} // namespace llvm::RISCV::mca
35+
} // namespace llvm::RISCV
4236

4337
namespace llvm {
4438
namespace mca {
@@ -268,35 +262,35 @@ unsigned RISCVInstrumentManager::getSchedClassID(
268262
uint8_t SEW = SI ? SI->getSEW() : 0;
269263

270264
std::optional<unsigned> VPOpcode;
271-
if (const auto *VXMO = RISCV::mca::getVXMemOpInfo(Opcode)) {
265+
if (const auto *VXMO = RISCV::getVXMemOpInfo(Opcode)) {
272266
// Calculate the expected index EMUL. For indexed operations,
273267
// the DataEEW and DataEMUL are equal to SEW and LMUL, respectively.
274268
unsigned IndexEMUL = ((1 << VXMO->Log2IdxEEW) * LMUL) / SEW;
275269

276270
if (!VXMO->NF) {
277271
// Indexed Load / Store.
278272
if (VXMO->IsStore) {
279-
if (const auto *VXP = RISCV::mca::getVSXPseudo(
273+
if (const auto *VXP = RISCV::getVSXPseudo(
280274
/*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
281275
IndexEMUL))
282276
VPOpcode = VXP->Pseudo;
283277
} else {
284-
if (const auto *VXP = RISCV::mca::getVLXPseudo(
278+
if (const auto *VXP = RISCV::getVLXPseudo(
285279
/*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
286280
IndexEMUL))
287281
VPOpcode = VXP->Pseudo;
288282
}
289283
} else {
290284
// Segmented Indexed Load / Store.
291285
if (VXMO->IsStore) {
292-
if (const auto *VXP = RISCV::mca::getVSXSEGPseudo(
293-
VXMO->NF, /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
294-
IndexEMUL))
286+
if (const auto *VXP =
287+
RISCV::getVSXSEGPseudo(VXMO->NF, /*Masked=*/0, VXMO->IsOrdered,
288+
VXMO->Log2IdxEEW, LMUL, IndexEMUL))
295289
VPOpcode = VXP->Pseudo;
296290
} else {
297-
if (const auto *VXP = RISCV::mca::getVLXSEGPseudo(
298-
VXMO->NF, /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
299-
IndexEMUL))
291+
if (const auto *VXP =
292+
RISCV::getVLXSEGPseudo(VXMO->NF, /*Masked=*/0, VXMO->IsOrdered,
293+
VXMO->Log2IdxEEW, LMUL, IndexEMUL))
300294
VPOpcode = VXP->Pseudo;
301295
}
302296
}

0 commit comments

Comments
 (0)