[AArch64] Regenerate aarch64-addv.ll test checks. NFC

Author: davemgreen

llvm/test/CodeGen/AArch64/aarch64-addv.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 -aarch64-neon-syntax=generic | FileCheck %s -check-prefixes=CHECK,SDAG
-; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -aarch64-neon-syntax=generic | FileCheck %s --check-prefixes=CHECK,GISEL
+; RUN: llc < %s -mtriple=aarch64 -aarch64-neon-syntax=generic | FileCheck %s -check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -aarch64-neon-syntax=generic | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
 declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8>)
@@ -247,26 +247,26 @@ entry:
 }
 
 define i8 @addv_v3i8(<3 x i8> %a) {
-; SDAG-LABEL: addv_v3i8:
-; SDAG:       // %bb.0: // %entry
-; SDAG-NEXT:    movi v0.2d, #0000000000000000
-; SDAG-NEXT:    mov v0.h[0], w0
-; SDAG-NEXT:    mov v0.h[1], w1
-; SDAG-NEXT:    mov v0.h[2], w2
-; SDAG-NEXT:    addv h0, v0.4h
-; SDAG-NEXT:    fmov w0, s0
-; SDAG-NEXT:    ret
+; CHECK-SD-LABEL: addv_v3i8:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT:    mov v0.h[0], w0
+; CHECK-SD-NEXT:    mov v0.h[1], w1
+; CHECK-SD-NEXT:    mov v0.h[2], w2
+; CHECK-SD-NEXT:    addv h0, v0.4h
+; CHECK-SD-NEXT:    fmov w0, s0
+; CHECK-SD-NEXT:    ret
 ;
-; GISEL-LABEL: addv_v3i8:
-; GISEL:       // %bb.0: // %entry
-; GISEL-NEXT:    fmov s0, w0
-; GISEL-NEXT:    mov w8, #0 // =0x0
-; GISEL-NEXT:    mov v0.h[1], w1
-; GISEL-NEXT:    mov v0.h[2], w2
-; GISEL-NEXT:    mov v0.h[3], w8
-; GISEL-NEXT:    addv h0, v0.4h
-; GISEL-NEXT:    fmov w0, s0
-; GISEL-NEXT:    ret
+; CHECK-GI-LABEL: addv_v3i8:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    fmov s0, w0
+; CHECK-GI-NEXT:    mov w8, #0 // =0x0
+; CHECK-GI-NEXT:    mov v0.h[1], w1
+; CHECK-GI-NEXT:    mov v0.h[2], w2
+; CHECK-GI-NEXT:    mov v0.h[3], w8
+; CHECK-GI-NEXT:    addv h0, v0.4h
+; CHECK-GI-NEXT:    fmov w0, s0
+; CHECK-GI-NEXT:    ret
 entry:
   %arg1 = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)
   ret i8 %arg1
@@ -329,22 +329,22 @@ entry:
 }
 
 define i16 @addv_v3i16(<3 x i16> %a) {
-; SDAG-LABEL: addv_v3i16:
-; SDAG:       // %bb.0: // %entry
-; SDAG-NEXT:    // kill: def $d0 killed $d0 def $q0
-; SDAG-NEXT:    mov v0.h[3], wzr
-; SDAG-NEXT:    addv h0, v0.4h
-; SDAG-NEXT:    fmov w0, s0
-; SDAG-NEXT:    ret
+; CHECK-SD-LABEL: addv_v3i16:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT:    mov v0.h[3], wzr
+; CHECK-SD-NEXT:    addv h0, v0.4h
+; CHECK-SD-NEXT:    fmov w0, s0
+; CHECK-SD-NEXT:    ret
 ;
-; GISEL-LABEL: addv_v3i16:
-; GISEL:       // %bb.0: // %entry
-; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT:    mov w8, #0 // =0x0
-; GISEL-NEXT:    mov v0.h[3], w8
-; GISEL-NEXT:    addv h0, v0.4h
-; GISEL-NEXT:    fmov w0, s0
-; GISEL-NEXT:    ret
+; CHECK-GI-LABEL: addv_v3i16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT:    mov w8, #0 // =0x0
+; CHECK-GI-NEXT:    mov v0.h[3], w8
+; CHECK-GI-NEXT:    addv h0, v0.4h
+; CHECK-GI-NEXT:    fmov w0, s0
+; CHECK-GI-NEXT:    ret
 entry:
   %arg1 = call i16 @llvm.vector.reduce.add.v3i16(<3 x i16> %a)
   ret i16 %arg1
@@ -442,29 +442,29 @@ entry:
 }
 
 define i64 @addv_v3i64(<3 x i64> %a) {
-; SDAG-LABEL: addv_v3i64:
-; SDAG:       // %bb.0: // %entry
-; SDAG-NEXT:    // kill: def $d2 killed $d2 def $q2
-; SDAG-NEXT:    // kill: def $d0 killed $d0 def $q0
-; SDAG-NEXT:    // kill: def $d1 killed $d1 def $q1
-; SDAG-NEXT:    mov v0.d[1], v1.d[0]
-; SDAG-NEXT:    mov v2.d[1], xzr
-; SDAG-NEXT:    add v0.2d, v0.2d, v2.2d
-; SDAG-NEXT:    addp d0, v0.2d
-; SDAG-NEXT:    fmov x0, d0
-; SDAG-NEXT:    ret
+; CHECK-SD-LABEL: addv_v3i64:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT:    mov v2.d[1], xzr
+; CHECK-SD-NEXT:    add v0.2d, v0.2d, v2.2d
+; CHECK-SD-NEXT:    addp d0, v0.2d
+; CHECK-SD-NEXT:    fmov x0, d0
+; CHECK-SD-NEXT:    ret
 ;
-; GISEL-LABEL: addv_v3i64:
-; GISEL:       // %bb.0: // %entry
-; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT:    // kill: def $d2 killed $d2 def $q2
-; GISEL-NEXT:    // kill: def $d1 killed $d1 def $q1
-; GISEL-NEXT:    mov v0.d[1], v1.d[0]
-; GISEL-NEXT:    mov v2.d[1], xzr
-; GISEL-NEXT:    add v0.2d, v0.2d, v2.2d
-; GISEL-NEXT:    addp d0, v0.2d
-; GISEL-NEXT:    fmov x0, d0
-; GISEL-NEXT:    ret
+; CHECK-GI-LABEL: addv_v3i64:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-GI-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT:    mov v2.d[1], xzr
+; CHECK-GI-NEXT:    add v0.2d, v0.2d, v2.2d
+; CHECK-GI-NEXT:    addp d0, v0.2d
+; CHECK-GI-NEXT:    fmov x0, d0
+; CHECK-GI-NEXT:    ret
 entry:
   %arg1 = call i64 @llvm.vector.reduce.add.v3i64(<3 x i64> %a)
   ret i64 %arg1
@@ -493,6 +493,3 @@ entry:
   ret i128 %arg1
 }
 
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL: {{.*}}
-; SDAG: {{.*}}