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fixup! [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension
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‎clang/include/clang/Basic/riscv_sifive_vector.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ multiclass RVVVCIXBuiltinSetWOSuffix<list<string> range, string prototype,
6161
}
6262

6363
let SupportOverloading = false in {
64-
defm sf_vc_x : RVVVCIXBuiltinSetWOSuffix<["i"], "0KzKzKzUeKzKz", [0, 3], UseGPR=1>;
64+
defm sf_vc_x : RVVVCIXBuiltinSetWOSuffix<["c", "s", "i", "l"], "0KzKzKzUeKzKz", [0, 3], UseGPR=1>;
6565
defm sf_vc_i : RVVVCIXBuiltinSetWOSuffix<["i"], "0KzKzKzKzKzKz", [2, 3], UseGPR=0>;
6666
defm sf_vc_xv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3], UseGPR=1>;
6767
defm sf_vc_iv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3], UseGPR=0>;

‎clang/lib/Headers/sifive_vector.h

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -14,37 +14,37 @@
1414
#pragma clang riscv intrinsic sifive_vector
1515

1616
#define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl) \
17-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 6, vl)
17+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 6, vl)
1818
#define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl) \
19-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 7, vl)
19+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 7, vl)
2020
#define __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl) \
21-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 0, vl)
21+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 0, vl)
2222
#define __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl) \
23-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 1, vl)
23+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 1, vl)
2424
#define __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl) \
25-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 2, vl)
25+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 2, vl)
2626
#define __riscv_sf_vc_x_se_u8m8(p27_26, p24_20, p11_7, rs1, vl) \
27-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 3, vl)
27+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 3, vl)
2828

2929
#define __riscv_sf_vc_x_se_u16mf2(p27_26, p24_20, p11_7, rs1, vl) \
30-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 7, vl)
30+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 7, vl)
3131
#define __riscv_sf_vc_x_se_u16m1(p27_26, p24_20, p11_7, rs1, vl) \
32-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 0, vl)
32+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 0, vl)
3333
#define __riscv_sf_vc_x_se_u16m2(p27_26, p24_20, p11_7, rs1, vl) \
34-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 1, vl)
34+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 1, vl)
3535
#define __riscv_sf_vc_x_se_u16m4(p27_26, p24_20, p11_7, rs1, vl) \
36-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 2, vl)
36+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 2, vl)
3737
#define __riscv_sf_vc_x_se_u16m8(p27_26, p24_20, p11_7, rs1, vl) \
38-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 3, vl)
38+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 3, vl)
3939

4040
#define __riscv_sf_vc_x_se_u32m1(p27_26, p24_20, p11_7, rs1, vl) \
41-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 0, vl)
41+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 0, vl)
4242
#define __riscv_sf_vc_x_se_u32m2(p27_26, p24_20, p11_7, rs1, vl) \
43-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 1, vl)
43+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 1, vl)
4444
#define __riscv_sf_vc_x_se_u32m4(p27_26, p24_20, p11_7, rs1, vl) \
45-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 2, vl)
45+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 2, vl)
4646
#define __riscv_sf_vc_x_se_u32m8(p27_26, p24_20, p11_7, rs1, vl) \
47-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 3, vl)
47+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 3, vl)
4848

4949
#define __riscv_sf_vc_i_se_u8mf4(p27_26, p24_20, p11_7, simm5, vl) \
5050
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 7, vl)
@@ -81,11 +81,11 @@
8181

8282
#if __riscv_v_elen >= 64
8383
#define __riscv_sf_vc_x_se_u8mf8(p27_26, p24_20, p11_7, rs1, vl) \
84-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 5, vl)
84+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 5, vl)
8585
#define __riscv_sf_vc_x_se_u16mf4(p27_26, p24_20, p11_7, rs1, vl) \
86-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 16, 6, vl)
86+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 6, vl)
8787
#define __riscv_sf_vc_x_se_u32mf2(p27_26, p24_20, p11_7, rs1, vl) \
88-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 32, 7, vl)
88+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 7, vl)
8989

9090
#define __riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7, simm5, vl) \
9191
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 5, vl)
@@ -105,13 +105,13 @@
105105

106106
#if __riscv_xlen >= 64
107107
#define __riscv_sf_vc_x_se_u64m1(p27_26, p24_20, p11_7, rs1, vl) \
108-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 0, vl)
108+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 0, vl)
109109
#define __riscv_sf_vc_x_se_u64m2(p27_26, p24_20, p11_7, rs1, vl) \
110-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 1, vl)
110+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 1, vl)
111111
#define __riscv_sf_vc_x_se_u64m4(p27_26, p24_20, p11_7, rs1, vl) \
112-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 2, vl)
112+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 2, vl)
113113
#define __riscv_sf_vc_x_se_u64m8(p27_26, p24_20, p11_7, rs1, vl) \
114-
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 64, 3, vl)
114+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 3, vl)
115115
#endif
116116
#endif
117117

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,7 @@
1010

1111
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1(
1212
// CHECK-RV64-NEXT: entry:
13-
// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32
14-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 0, i64 [[VL:%.*]])
13+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 0, i64 [[VL:%.*]])
1514
// CHECK-RV64-NEXT: ret void
1615
//
1716
void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
@@ -20,8 +19,7 @@ void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
2019

2120
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m2(
2221
// CHECK-RV64-NEXT: entry:
23-
// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32
24-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 1, i64 [[VL:%.*]])
22+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 1, i64 [[VL:%.*]])
2523
// CHECK-RV64-NEXT: ret void
2624
//
2725
void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) {
@@ -30,8 +28,7 @@ void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) {
3028

3129
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m4(
3230
// CHECK-RV64-NEXT: entry:
33-
// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32
34-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 2, i64 [[VL:%.*]])
31+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 2, i64 [[VL:%.*]])
3532
// CHECK-RV64-NEXT: ret void
3633
//
3734
void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) {
@@ -40,8 +37,7 @@ void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) {
4037

4138
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m8(
4239
// CHECK-RV64-NEXT: entry:
43-
// CHECK-RV64-NEXT: [[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32
44-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[CONV]], i64 64, i64 3, i64 [[VL:%.*]])
40+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 3, i64 [[VL:%.*]])
4541
// CHECK-RV64-NEXT: ret void
4642
//
4743
void test_sf_vc_x_se_u64m8(uint64_t rs1, size_t vl) {

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