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AMDGPU: Cleanup extract_subvector actions (NFC) (#101454)
The base AMDGPUISelLowering was setting custom action on 16-bit vector types, but also set in SIISelLowering.
1 parent e167f75 commit 1d2b2d2

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2 files changed

+7
-11
lines changed

2 files changed

+7
-11
lines changed

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -444,19 +444,15 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
444444
MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32},
445445
Custom);
446446

447-
// FIXME: Why is v8f16/v8bf16 missing?
448447
setOperationAction(
449448
ISD::EXTRACT_SUBVECTOR,
450-
{MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4f16, MVT::v4bf16,
451-
MVT::v4i16, MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32,
452-
MVT::v4f32, MVT::v4i32, MVT::v5f32, MVT::v5i32, MVT::v6f32,
453-
MVT::v6i32, MVT::v7f32, MVT::v7i32, MVT::v8f32, MVT::v8i32,
454-
MVT::v9f32, MVT::v9i32, MVT::v10i32, MVT::v10f32, MVT::v11i32,
455-
MVT::v11f32, MVT::v12i32, MVT::v12f32, MVT::v16f16, MVT::v16bf16,
456-
MVT::v16i16, MVT::v16f32, MVT::v16i32, MVT::v32f32, MVT::v32i32,
449+
{MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32, MVT::v4f32,
450+
MVT::v4i32, MVT::v5f32, MVT::v5i32, MVT::v6f32, MVT::v6i32,
451+
MVT::v7f32, MVT::v7i32, MVT::v8f32, MVT::v8i32, MVT::v9f32,
452+
MVT::v9i32, MVT::v10i32, MVT::v10f32, MVT::v11i32, MVT::v11f32,
453+
MVT::v12i32, MVT::v12f32, MVT::v16i32, MVT::v32f32, MVT::v32i32,
457454
MVT::v2f64, MVT::v2i64, MVT::v3f64, MVT::v3i64, MVT::v4f64,
458-
MVT::v4i64, MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64,
459-
MVT::v32i16, MVT::v32f16, MVT::v32bf16},
455+
MVT::v4i64, MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64},
460456
Custom);
461457

462458
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -629,10 +629,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
629629
case ISD::EXTRACT_VECTOR_ELT:
630630
case ISD::INSERT_VECTOR_ELT:
631631
case ISD::INSERT_SUBVECTOR:
632-
case ISD::EXTRACT_SUBVECTOR:
633632
case ISD::SCALAR_TO_VECTOR:
634633
case ISD::IS_FPCLASS:
635634
break;
635+
case ISD::EXTRACT_SUBVECTOR:
636636
case ISD::CONCAT_VECTORS:
637637
setOperationAction(Op, VT, Custom);
638638
break;

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