Add V75 support to compiler and assembler

This patch introduces support for the Hexagon V75 architecture.
It includes instruction formats, definitions, encodings, scheduling classes,
and builtins/intrinsics.

Author: iajbar

clang/include/clang/Basic/BuiltinsHexagon.def

@@ -17,8 +17,10 @@
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
+#pragma push_macro("V75")
+#define V75 "v75"
 #pragma push_macro("V73")
-#define V73 "v73"
+#define V73 "v73|" V75
 #pragma push_macro("V71")
 #define V71 "v71|" V73
 #pragma push_macro("V69")
@@ -40,8 +42,10 @@
 #pragma push_macro("V5")
 #define V5 "v5|" V55
 
+#pragma push_macro("HVXV75")
+#define HVXV75 "hvxv75"
 #pragma push_macro("HVXV73")
-#define HVXV73 "hvxv73"
+#define HVXV73 "hvxv73|" HVXV75
 #pragma push_macro("HVXV71")
 #define HVXV71 "hvxv71|" HVXV73
 #pragma push_macro("HVXV69")
@@ -143,6 +147,7 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("HVXV69")
 #pragma pop_macro("HVXV71")
 #pragma pop_macro("HVXV73")
+#pragma pop_macro("HVXV75")
 
 #pragma pop_macro("V5")
 #pragma pop_macro("V55")
@@ -155,6 +160,7 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("V69")
 #pragma pop_macro("V71")
 #pragma pop_macro("V73")
+#pragma pop_macro("V75")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Driver/Options.td

@@ -6224,6 +6224,8 @@ def mv71t : Flag<["-"], "mv71t">, Group<m_hexagon_Features_Group>,
   Alias<mcpu_EQ>, AliasArgs<["hexagonv71t"]>;
 def mv73 : Flag<["-"], "mv73">, Group<m_hexagon_Features_Group>,
   Alias<mcpu_EQ>, AliasArgs<["hexagonv73"]>;
+def mv75 : Flag<["-"], "mv75">, Group<m_hexagon_Features_Group>,
+  Alias<mcpu_EQ>, AliasArgs<["hexagonv75"]>;
 def mhexagon_hvx : Flag<["-"], "mhvx">, Group<m_hexagon_Features_HVX_Group>,
   HelpText<"Enable Hexagon Vector eXtensions">;
 def mhexagon_hvx_EQ : Joined<["-"], "mhvx=">,

clang/lib/Basic/Targets/Hexagon.cpp

@@ -78,6 +78,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
   } else if (CPU == "hexagonv73") {
     Builder.defineMacro("__HEXAGON_V73__");
     Builder.defineMacro("__HEXAGON_ARCH__", "73");
+  } else if (CPU == "hexagonv75") {
+    Builder.defineMacro("__HEXAGON_V75__");
+    Builder.defineMacro("__HEXAGON_ARCH__", "75");
   }
 
   if (hasFeature("hvx-length64b")) {
@@ -234,8 +237,8 @@ static constexpr CPUSuffix Suffixes[] = {
     {{"hexagonv65"}, {"65"}}, {{"hexagonv66"},  {"66"}},
     {{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
     {{"hexagonv68"}, {"68"}}, {{"hexagonv69"},  {"69"}},
-    {{"hexagonv71"}, {"71"}}, {{"hexagonv71t"},  {"71t"}},
-    {{"hexagonv73"}, {"73"}},
+    {{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
+    {{"hexagonv73"}, {"73"}}, {{"hexagonv75"},  {"75"}},
 };
 
 std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {

clang/test/Driver/hexagon-toolchain-elf.c

@@ -152,6 +152,13 @@
 // CHECK230: "-cc1" {{.*}} "-target-cpu" "hexagonv73"
 // CHECK230: hexagon-link{{.*}}/Inputs/hexagon_tree/Tools/bin/../target/hexagon/lib/v73/crt0
 
+// RUN: not %clang -### --target=hexagon-unknown-elf \
+// RUN:   -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \
+// RUN:   -mcpu=hexagonv75 -fuse-ld=hexagon-link \
+// RUN:   %s 2>&1 | FileCheck -check-prefix=CHECK240 %s
+// CHECK240: "-cc1" {{.*}} "-target-cpu" "hexagonv75"
+// CHECK240: hexagon-link{{.*}}/Inputs/hexagon_tree/Tools/bin/../target/hexagon/lib/v75/crt0
+
 // -----------------------------------------------------------------------------
 // Test Linker related args
 // -----------------------------------------------------------------------------

clang/test/Misc/target-invalid-cpu-note/hexagon.c

@@ -18,4 +18,5 @@
 // CHECK-SAME: {{^}}, hexagonv71
 // CHECK-SAME: {{^}}, hexagonv71t
 // CHECK-SAME: {{^}}, hexagonv73
+// CHECK-SAME: {{^}}, hexagonv75
 // CHECK-SAME: {{$}}

clang/test/Preprocessor/hexagon-predefines.c

@@ -137,6 +137,22 @@
 // CHECK-V73HVX-128B: #define __HVX__ 1
 // CHECK-V73HVX-128B: #define __hexagon__ 1
 
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv75 %s\
+// RUN: | FileCheck %s -check-prefix CHECK-V75
+// CHECK-V75: #define __HEXAGON_ARCH__ 75
+// CHECK-V75: #define __HEXAGON_PHYSICAL_SLOTS__ 4
+// CHECK-V75: #define __HEXAGON_V75__ 1
+// CHECK-V75: #define __hexagon__ 1
+
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv75 \
+// RUN: -target-feature +hvxv75 -target-feature +hvx-length128b %s | FileCheck \
+// RUN: %s -check-prefix CHECK-V75HVX-128B
+// CHECK-V75HVX-128B: #define __HEXAGON_ARCH__ 75
+// CHECK-V75HVX-128B: #define __HEXAGON_V75__ 1
+// CHECK-V75HVX-128B: #define __HVX_ARCH__ 75
+// CHECK-V75HVX-128B: #define __HVX_LENGTH__ 128
+// CHECK-V75HVX-128B: #define __HVX__ 1
+// CHECK-V75HVX-128B: #define __hexagon__ 1
 
 // RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv67 \
 // RUN: -target-feature +hvxv67 -target-feature +hvx-length128b %s | FileCheck \

llvm/include/llvm/BinaryFormat/ELF.h

@@ -629,6 +629,7 @@ enum {
   EF_HEXAGON_MACH_V71 = 0x00000071,  // Hexagon V71
   EF_HEXAGON_MACH_V71T = 0x00008071, // Hexagon V71T
   EF_HEXAGON_MACH_V73 = 0x00000073,  // Hexagon V73
+  EF_HEXAGON_MACH_V75 = 0x00000075,  // Hexagon V75
   EF_HEXAGON_MACH = 0x000003ff,      // Hexagon V..
 
   // Highest ISA version flags

llvm/lib/Object/ELFObjectFile.cpp

@@ -309,6 +309,8 @@ static std::optional<std::string> hexagonAttrToFeatureString(unsigned Attr) {
     return "v71";
   case 73:
     return "v73";
+  case 75:
+    return "v75";
   default:
     return {};
   }

llvm/lib/ObjectYAML/ELFYAML.cpp

@@ -496,6 +496,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
     BCaseMask(EF_HEXAGON_MACH_V71, EF_HEXAGON_MACH);
     BCaseMask(EF_HEXAGON_MACH_V71T, EF_HEXAGON_MACH);
     BCaseMask(EF_HEXAGON_MACH_V73, EF_HEXAGON_MACH);
+    BCaseMask(EF_HEXAGON_MACH_V75, EF_HEXAGON_MACH);
     BCaseMask(EF_HEXAGON_ISA_V2, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V3, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V4, EF_HEXAGON_ISA);
@@ -510,6 +511,7 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
     BCaseMask(EF_HEXAGON_ISA_V69, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V71, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V73, EF_HEXAGON_ISA);
+    BCaseMask(EF_HEXAGON_ISA_V75, EF_HEXAGON_ISA);
     break;
   case ELF::EM_AVR:
     BCaseMask(EF_AVR_ARCH_AVR1, EF_AVR_ARCH_MASK);

llvm/lib/Target/Hexagon/Hexagon.td

@@ -67,6 +67,12 @@ def ExtensionHVXV73: SubtargetFeature<"hvxv73", "HexagonHVXVersion",
       [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
        ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71]>;
 
+def ExtensionHVXV75: SubtargetFeature<"hvxv75", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V75", "Hexagon HVX instructions",
+      [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
+       ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
+       ExtensionHVXV73]>;
+
 def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
       "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
 def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
@@ -137,6 +143,8 @@ def UseHVXV71          : Predicate<"HST->useHVXV71Ops()">,
                          AssemblerPredicate<(all_of ExtensionHVXV71)>;
 def UseHVXV73          : Predicate<"HST->useHVXV73Ops()">,
                          AssemblerPredicate<(all_of ExtensionHVXV73)>;
+def UseHVXV75          : Predicate<"HST->useHVXV75Ops()">,
+                         AssemblerPredicate<(all_of ExtensionHVXV75)>;
 def UseAudio           : Predicate<"HST->useAudioOps()">,
                          AssemblerPredicate<(all_of ExtensionAudio)>;
 def UseZReg            : Predicate<"HST->useZRegOps()">,
@@ -462,6 +470,12 @@ def : Proc<"hexagonv73", HexagonModelV73,
             ArchV68, ArchV69, ArchV71, ArchV73,
             FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
             FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
+def : Proc<"hexagonv75", HexagonModelV75,
+           [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
+           ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, FeatureCompound,
+           FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
+           FeatureNVS, FeaturePackets, FeatureSmallData]>;
+
 // Need to update the correct features for tiny core.
 // Disable NewValueJumps since the packetizer is unable to handle a packet with
 // a new value jump and another SLOT0 instruction.

llvm/lib/Target/Hexagon/HexagonDepArch.h

@@ -27,7 +27,8 @@ enum class ArchEnum {
   V68,
   V69,
   V71,
-  V73
+  V73,
+  V75
 };
 
 inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
@@ -46,6 +47,7 @@ inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
       .Case("hexagonv71", Hexagon::ArchEnum::V71)
       .Case("hexagonv71t", Hexagon::ArchEnum::V71)
       .Case("hexagonv73", Hexagon::ArchEnum::V73)
+      .Case("hexagonv75", Hexagon::ArchEnum::V75)
       .Default(std::nullopt);
 }
 } // namespace Hexagon

llvm/lib/Target/Hexagon/HexagonDepArch.td

@@ -30,3 +30,5 @@ def ArchV71: SubtargetFeature<"v71", "HexagonArchVersion", "Hexagon::ArchEnum::V
 def HasV71 : Predicate<"HST->hasV71Ops()">, AssemblerPredicate<(all_of ArchV71)>;
 def ArchV73: SubtargetFeature<"v73", "HexagonArchVersion", "Hexagon::ArchEnum::V73", "Enable Hexagon V73 architecture">;
 def HasV73 : Predicate<"HST->hasV73Ops()">, AssemblerPredicate<(all_of ArchV73)>;
+def ArchV75: SubtargetFeature<"v75", "HexagonArchVersion", "Hexagon::ArchEnum::V75", "Enable Hexagon V75 architecture">;
+def HasV75 : Predicate<"HST->hasV75Ops()">, AssemblerPredicate<(all_of ArchV75)>;