Skip to content

Commit 1da9354

Browse files
committed
Remove commented out table entries
1 parent f1a47b7 commit 1da9354

File tree

2 files changed

+3
-9
lines changed

2 files changed

+3
-9
lines changed

clang/include/clang/Basic/arm_sme.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -299,6 +299,9 @@ multiclass ZAAddSub<string n_suffix> {
299299
defm SVADD : ZAAddSub<"add">;
300300
defm SVSUB : ZAAddSub<"sub">;
301301

302+
//
303+
// Spill and fill of ZT0
304+
//
302305
let TargetGuard = "sme2" in {
303306
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;
304307
def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;

clang/include/clang/Basic/arm_sve.td

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1813,15 +1813,6 @@ def SVWHILERW_H_BF16 : SInst<"svwhilerw[_{1}]", "Pcc", "b", MergeNone, "aarch64_
18131813
def SVWHILEWR_H_BF16 : SInst<"svwhilewr[_{1}]", "Pcc", "b", MergeNone, "aarch64_sve_whilewr_h", [IsOverloadWhileRW]>;
18141814
}
18151815

1816-
// //
1817-
// // Spill and fill of ZT0
1818-
// //
1819-
1820-
// let TargetGuard = "sme2" in {
1821-
// def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;
1822-
// def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;
1823-
// }
1824-
18251816
////////////////////////////////////////////////////////////////////////////////
18261817
// SVE2 - Extended table lookup/permute
18271818
let TargetGuard = "sve2" in {

0 commit comments

Comments
 (0)