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nikolaypanchenkonikolaypanchenko
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Fixed typos in cmake file and added more tests
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3 files changed

+151
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‎mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -73,9 +73,9 @@ mlir_tablegen(ROCDLOpsAttributes.cpp.inc -gen-attrdef-defs -attrdefs-dialect=roc
7373
add_public_tablegen_target(MLIRROCDLConversionsIncGen)
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7575
add_mlir_dialect(VCIXOps vcix)
76-
add_mlir_doc(VCIXOps RVCIXDialect Dialects/ -gen-dialect-doc -dialect=rocdl)
76+
add_mlir_doc(VCIXOps VCIXDialect Dialects/ -gen-dialect-doc -dialect=vcix)
7777
set(LLVM_TARGET_DEFINITIONS VCIXOps.td)
7878
mlir_tablegen(VCIXConversions.inc -gen-llvmir-conversions)
79-
mlir_tablegen(VCIXOpsAttributes.h.inc -gen-attrdef-decls -attrdefs-dialect=rocdl)
80-
mlir_tablegen(VCIXOpsAttributes.cpp.inc -gen-attrdef-defs -attrdefs-dialect=rocdl)
79+
mlir_tablegen(VCIXOpsAttributes.h.inc -gen-attrdef-decls -attrdefs-dialect=vcix)
80+
mlir_tablegen(VCIXOpsAttributes.cpp.inc -gen-attrdef-defs -attrdefs-dialect=vcix)
8181
add_public_tablegen_target(MLIRVCIXConversionsIncGen)

‎mlir/test/Target/LLVMIR/vcix-rv32.mlir

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,3 +71,77 @@ llvm.func @binary_fixed_iv(%arg0: vector<4xf32>, %rd: i32) -> vector<4xf32> {
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%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<4xf32>, i32) -> vector<4xf32>
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llvm.return %0 : vector<4xf32>
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}
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// Test integer type
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// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_fv(<vscale x 4 x i32> %0, float %1, i32 %2) {
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// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv4i32.i32.nxv4i32.f32.i32(i32 1, <vscale x 4 x i32> %0, float %1, i32 %2)
79+
// CHECK-NEXT: ret <vscale x 4 x i32> %4
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// CHECK-NEXT: }
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llvm.func @binary_i_fv(%arg0: vector<[4]xi32>, %arg1: f32, %vl: i32) -> vector<[4]xi32> {
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%0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 1 : i32}> : (vector<[4]xi32>, f32, i32) -> vector<[4]xi32>
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llvm.return %0 : vector<[4]xi32>
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}
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// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_xv(<vscale x 4 x i32> %0, i32 %1, i32 %2) {
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// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> %0, i32 %1, i32 %2)
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// CHECK-NEXT: ret <vscale x 4 x i32> %4
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// CHECK-NEXT: }
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llvm.func @binary_i_xv(%arg0: vector<[4]xi32>, %arg1: i32, %vl: i32) -> vector<[4]xi32> {
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%0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i32}> : (vector<[4]xi32>, i32, i32) -> vector<[4]xi32>
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llvm.return %0 : vector<[4]xi32>
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}
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// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_vv(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) {
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// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv4i32.i32.nxv4i32.nxv4i32.i32(i32 3, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2)
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// CHECK-NEXT: ret <vscale x 4 x i32> %4
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// CHECK-NEXT: }
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llvm.func @binary_i_vv(%arg0: vector<[4]xi32>, %arg1: vector<[4]xi32>, %vl: i32) -> vector<[4]xi32> {
100+
%0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i32}> : (vector<[4]xi32>, vector<[4]xi32>, i32) -> vector<[4]xi32>
101+
llvm.return %0 : vector<[4]xi32>
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}
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// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_iv(<vscale x 4 x i32> %0, i32 %1, i32 %2) {
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// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> %0, i32 5, i32 %2)
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// CHECK-NEXT: ret <vscale x 4 x i32> %4
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// CHECK-NEXT: }
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llvm.func @binary_i_iv(%arg0: vector<[4]xi32>, %rd: i32, %vl: i32) -> vector<[4]xi32> {
109+
%0 = "vcix.v.iv"(%arg0, %rd, %vl) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<[4]xi32>, i32, i32) -> vector<[4]xi32>
110+
llvm.return %0 : vector<[4]xi32>
111+
}
112+
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// CHECK-LABEL: define <4 x i32> @binary_i_fixed_fv(<4 x i32> %0, float %1) {
114+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.fv.se.v4i32.i32.v4i32.f32.i32(i32 1, <4 x i32> %0, float %1, i32 4)
115+
// CHECK-NEXT: ret <4 x i32> %3
116+
// CHECK-NEXT: }
117+
llvm.func @binary_i_fixed_fv(%arg0: vector<4xi32>, %arg1: f32) -> vector<4xi32> {
118+
%0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 1 : i32}> : (vector<4xi32>, f32) -> vector<4xi32>
119+
llvm.return %0 : vector<4xi32>
120+
}
121+
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// CHECK-LABEL: define <4 x i32> @binary_i_fixed_xv(<4 x i32> %0, i32 %1) {
123+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.xv.se.v4i32.i32.v4i32.i32.i32(i32 3, <4 x i32> %0, i32 %1, i32 4)
124+
// CHECK-NEXT: ret <4 x i32> %3
125+
// CHECK-NEXT: }
126+
llvm.func @binary_i_fixed_xv(%arg0: vector<4xi32>, %arg1: i32) -> vector<4xi32> {
127+
%0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i32}> : (vector<4xi32>, i32) -> vector<4xi32>
128+
llvm.return %0 : vector<4xi32>
129+
}
130+
131+
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_vv(<4 x i32> %0, <4 x i32> %1) {
132+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.vv.se.v4i32.i32.v4i32.v4i32.i32(i32 3, <4 x i32> %0, <4 x i32> %1, i32 4)
133+
// CHECK-NEXT: ret <4 x i32> %3
134+
// CHECK-NEXT: }
135+
llvm.func @binary_i_fixed_vv(%arg0: vector<4xi32>, %arg1: vector<4xi32>) -> vector<4xi32> {
136+
%0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i32}> : (vector<4xi32>, vector<4xi32>) -> vector<4xi32>
137+
llvm.return %0 : vector<4xi32>
138+
}
139+
140+
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_iv(<4 x i32> %0, i32 %1) {
141+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.iv.se.v4i32.i32.v4i32.i32.i32(i32 3, <4 x i32> %0, i32 5, i32 4)
142+
// CHECK-NEXT: ret <4 x i32> %3
143+
// CHECK-NEXT: }
144+
llvm.func @binary_i_fixed_iv(%arg0: vector<4xi32>, %rd: i32) -> vector<4xi32> {
145+
%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<4xi32>, i32) -> vector<4xi32>
146+
llvm.return %0 : vector<4xi32>
147+
}

‎mlir/test/Target/LLVMIR/vcix-rv64.mlir

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,3 +72,77 @@ llvm.func @binary_fixed_iv(%arg0: vector<4xf32>, %rd: i64) -> vector<4xf32> {
7272
%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xf32>, i64) -> vector<4xf32>
7373
llvm.return %0 : vector<4xf32>
7474
}
75+
76+
// Test integer type
77+
78+
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_fv(<vscale x 4 x i32> %0, float %1, i64 %2) {
79+
// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv4i32.i64.nxv4i32.f32.i64(i64 1, <vscale x 4 x i32> %0, float %1, i64 %2)
80+
// CHECK-NEXT: ret <vscale x 4 x i32> %4
81+
// CHECK-NEXT: }
82+
llvm.func @binary_i_fv(%arg0: vector<[4]xi32>, %arg1: f32, %vl: i64) -> vector<[4]xi32> {
83+
%0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 1 : i64}> : (vector<[4]xi32>, f32, i64) -> vector<[4]xi32>
84+
llvm.return %0 : vector<[4]xi32>
85+
}
86+
87+
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_xv(<vscale x 4 x i32> %0, i64 %1, i64 %2) {
88+
// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> %0, i64 %1, i64 %2)
89+
// CHECK-NEXT: ret <vscale x 4 x i32> %4
90+
// CHECK-NEXT: }
91+
llvm.func @binary_i_xv(%arg0: vector<[4]xi32>, %arg1: i64, %vl: i64) -> vector<[4]xi32> {
92+
%0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i64}> : (vector<[4]xi32>, i64, i64) -> vector<[4]xi32>
93+
llvm.return %0 : vector<[4]xi32>
94+
}
95+
96+
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_vv(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) {
97+
// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv4i32.i64.nxv4i32.nxv4i32.i64(i64 3, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
98+
// CHECK-NEXT: ret <vscale x 4 x i32> %4
99+
// CHECK-NEXT: }
100+
llvm.func @binary_i_vv(%arg0: vector<[4]xi32>, %arg1: vector<[4]xi32>, %vl: i64) -> vector<[4]xi32> {
101+
%0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i64}> : (vector<[4]xi32>, vector<[4]xi32>, i64) -> vector<[4]xi32>
102+
llvm.return %0 : vector<[4]xi32>
103+
}
104+
105+
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_iv(<vscale x 4 x i32> %0, i64 %1, i64 %2) {
106+
// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> %0, i64 5, i64 %2)
107+
// CHECK-NEXT: ret <vscale x 4 x i32> %4
108+
// CHECK-NEXT: }
109+
llvm.func @binary_i_iv(%arg0: vector<[4]xi32>, %rd: i64, %vl: i64) -> vector<[4]xi32> {
110+
%0 = "vcix.v.iv"(%arg0, %rd, %vl) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<[4]xi32>, i64, i64) -> vector<[4]xi32>
111+
llvm.return %0 : vector<[4]xi32>
112+
}
113+
114+
// CHECK: define <4 x i32> @binary_i_fixed_fv(<4 x i32> %0, float %1) {
115+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.fv.se.v4i32.i64.v4i32.f32.i64(i64 1, <4 x i32> %0, float %1, i64 4)
116+
// CHECK-NEXT: ret <4 x i32> %3
117+
// CHECK-NEXT: }
118+
llvm.func @binary_i_fixed_fv(%arg0: vector<4xi32>, %arg1: f32) -> vector<4xi32> {
119+
%0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 1 : i64}> : (vector<4xi32>, f32) -> vector<4xi32>
120+
llvm.return %0 : vector<4xi32>
121+
}
122+
123+
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_xv(<4 x i32> %0, i64 %1) {
124+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.xv.se.v4i32.i64.v4i32.i64.i64(i64 3, <4 x i32> %0, i64 %1, i64 4)
125+
// CHECK-NEXT: ret <4 x i32> %3
126+
// CHECK-NEXT: }
127+
llvm.func @binary_i_fixed_xv(%arg0: vector<4xi32>, %arg1: i64) -> vector<4xi32> {
128+
%0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i64}> : (vector<4xi32>, i64) -> vector<4xi32>
129+
llvm.return %0 : vector<4xi32>
130+
}
131+
132+
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_vv(<4 x i32> %0, <4 x i32> %1) {
133+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.vv.se.v4i32.i64.v4i32.v4i32.i64(i64 3, <4 x i32> %0, <4 x i32> %1, i64 4)
134+
// CHECK-NEXT: ret <4 x i32> %3
135+
// CHECK-NEXT: }
136+
llvm.func @binary_i_fixed_vv(%arg0: vector<4xi32>, %arg1: vector<4xi32>) -> vector<4xi32> {
137+
%0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i64}> : (vector<4xi32>, vector<4xi32>) -> vector<4xi32>
138+
llvm.return %0 : vector<4xi32>
139+
}
140+
141+
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_iv(<4 x i32> %0, i64 %1) {
142+
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.iv.se.v4i32.i64.v4i32.i64.i64(i64 3, <4 x i32> %0, i64 5, i64 4)
143+
// CHECK-NEXT: ret <4 x i32> %3
144+
// CHECK-NEXT: }
145+
llvm.func @binary_i_fixed_iv(%arg0: vector<4xi32>, %rd: i64) -> vector<4xi32> {
146+
%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xi32>, i64) -> vector<4xi32>
147+
llvm.return %0 : vector<4xi32>
148+
}

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