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[RISCV][llvm-mca] Add mca tests for riscv lmul instruments
Add llvm-mca tests for RISCV LMUL instruments to show that llvm-mca RISCV LMUL instruments work. Differential Revision: https://reviews.llvm.org/D149496
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‎llvm/test/tools/llvm-mca/RISCV/different-instruments.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
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vsetvli zero, a0, e8, m1, tu, mu
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# LLVM-MCA-RISCV-LMUL M1
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vadd.vv v12, v12, v12
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vsetvli zero, a0, e8, m8, tu, mu
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# LLVM-MCA-RISCV-LMUL M8
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vadd.vv v12, v12, v12
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 4
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# CHECK-NEXT: Total Cycles: 12
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# CHECK-NEXT: Total uOps: 4
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.33
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# CHECK-NEXT: IPC: 0.33
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# CHECK-NEXT: Block RThroughput: 18.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFive7FDiv
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# CHECK-NEXT: [1] - SiFive7IDiv
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# CHECK-NEXT: [2] - SiFive7PipeA
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# CHECK-NEXT: [3] - SiFive7PipeB
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# CHECK-NEXT: [4] - SiFive7PipeV
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# CHECK-NEXT: [5] - SiFive7VA
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# CHECK-NEXT: [6] - SiFive7VL
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# CHECK-NEXT: [7] - SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 2.00 - 18.00 18.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
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# CHECK: Timeline view:
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# CHECK-NEXT: 01
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# CHECK-NEXT: Index 0123456789
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# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12
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# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

‎llvm/test/tools/llvm-mca/RISCV/disable-im.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 -disable-im < %s | FileCheck %s
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vsetvli zero, a0, e8, m2, tu, mu
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# LLVM-MCA-RISCV-LMUL M2
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vadd.vv v12, v12, v12
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vsetvli zero, a0, e8, m1, tu, mu
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# LLVM-MCA-RISCV-LMUL M1
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vadd.vv v12, v12, v12
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vsetvli zero, a0, e8, m8, tu, mu
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# LLVM-MCA-RISCV-LMUL M8
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vadd.vv v12, v12, v12
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 6
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# CHECK-NEXT: Total Cycles: 40
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# CHECK-NEXT: Total uOps: 6
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.15
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# CHECK-NEXT: IPC: 0.15
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# CHECK-NEXT: Block RThroughput: 48.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFive7FDiv
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# CHECK-NEXT: [1] - SiFive7IDiv
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# CHECK-NEXT: [2] - SiFive7PipeA
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# CHECK-NEXT: [3] - SiFive7PipeB
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# CHECK-NEXT: [4] - SiFive7PipeV
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# CHECK-NEXT: [5] - SiFive7VA
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# CHECK-NEXT: [6] - SiFive7VL
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# CHECK-NEXT: [7] - SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 3.00 - 48.00 48.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu
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# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
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# CHECK: Timeline view:
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# CHECK-NEXT: 0123456789 0123456789
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# CHECK-NEXT: Index 0123456789 0123456789
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# CHECK: [0,0] DeeE . . . . . . . . vsetvli zero, a0, e8, m2, tu, mu
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# CHECK-NEXT: [0,1] . DeeeE . . . . . . . vadd.vv v12, v12, v12
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# CHECK-NEXT: [0,2] . DeeE . . . . . . . vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: [0,3] . . . . DeeeE . . . . vadd.vv v12, v12, v12
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# CHECK-NEXT: [0,4] . . . . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: [0,5] . . . . . . . DeeeE vadd.vv v12, v12, v12
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

‎llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
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vsetvli zero, a0, e8, m1, tu, mu
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# LLVM-MCA-RISCV-LMUL M1
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vadd.vv v12, v12, v12
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 2
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# CHECK-NEXT: Total Cycles: 8
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# CHECK-NEXT: Total uOps: 2
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.25
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# CHECK-NEXT: IPC: 0.25
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# CHECK-NEXT: Block RThroughput: 2.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFive7FDiv
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# CHECK-NEXT: [1] - SiFive7IDiv
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# CHECK-NEXT: [2] - SiFive7PipeA
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# CHECK-NEXT: [3] - SiFive7PipeB
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# CHECK-NEXT: [4] - SiFive7PipeV
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# CHECK-NEXT: [5] - SiFive7VA
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# CHECK-NEXT: [6] - SiFive7VL
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# CHECK-NEXT: [7] - SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 01234567
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# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

‎llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
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vadd.vv v12, v12, v12
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vsetvli zero, a0, e8, m8, tu, mu
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# LLVM-MCA-RISCV-LMUL MF8
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vadd.vv v12, v12, v12
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 3
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# CHECK-NEXT: Total Cycles: 21
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# CHECK-NEXT: Total uOps: 3
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.14
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# CHECK-NEXT: IPC: 0.14
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# CHECK-NEXT: Block RThroughput: 17.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFive7FDiv
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# CHECK-NEXT: [1] - SiFive7IDiv
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# CHECK-NEXT: [2] - SiFive7PipeA
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# CHECK-NEXT: [3] - SiFive7PipeB
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# CHECK-NEXT: [4] - SiFive7PipeV
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# CHECK-NEXT: [5] - SiFive7VA
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# CHECK-NEXT: [6] - SiFive7VL
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# CHECK-NEXT: [7] - SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 1.00 - 17.00 17.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12
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# CHECK: Timeline view:
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# CHECK-NEXT: 0123456789
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# CHECK-NEXT: Index 0123456789 0
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# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
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# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
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# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

‎llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
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# LLVM-MCA-BEGIN foo
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vsetvli zero, a0, e8, m1, tu, mu
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# LLVM-MCA-RISCV-LMUL M1
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vadd.vv v12, v12, v12
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# LLVM-MCA-END foo
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# CHECK: [0] Code Region - foo
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 2
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# CHECK-NEXT: Total Cycles: 8
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# CHECK-NEXT: Total uOps: 2
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.25
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# CHECK-NEXT: IPC: 0.25
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# CHECK-NEXT: Block RThroughput: 2.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFive7FDiv
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# CHECK-NEXT: [1] - SiFive7IDiv
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# CHECK-NEXT: [2] - SiFive7PipeA
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# CHECK-NEXT: [3] - SiFive7PipeB
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# CHECK-NEXT: [4] - SiFive7PipeV
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# CHECK-NEXT: [5] - SiFive7VA
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# CHECK-NEXT: [6] - SiFive7VL
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# CHECK-NEXT: [7] - SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 01234567
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# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
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# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

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