Address review comments

Author: KanRobert

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

@@ -4001,7 +4001,7 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
 
   if (UseApxExtendedReg && !X86II::canUseApxExtendedReg(MCID))
     return Match_Unsupported;
-  if (ForcedNoFlag != static_cast<bool>(MCID.TSFlags & X86II::EVEX_NF))
+  if (ForcedNoFlag != !!(MCID.TSFlags & X86II::EVEX_NF))
     return Match_Unsupported;
 
   if (ForcedVEXEncoding == VEXEncoding_EVEX &&

llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

@@ -996,7 +996,7 @@ inline unsigned getOperandBias(const MCInstrDesc &Desc) {
 }
 
 /// \returns true if the instruction has a NDD (new data destination).
-inline bool isND(uint64_t TSFlags) {
+inline bool hasNewDataDestination(uint64_t TSFlags) {
   return (TSFlags & X86II::OpMapMask) == X86II::T_MAP4 &&
          (TSFlags & X86II::EVEX_B) && (TSFlags & X86II::VEX_4V);
 }
@@ -1027,7 +1027,7 @@ inline int getMemoryOperandNo(uint64_t TSFlags) {
     return -1;
   case X86II::MRMDestMem:
   case X86II::MRMDestMemFSIB:
-    return isND(TSFlags);
+    return hasNewDataDestination(TSFlags);
   case X86II::MRMSrcMem:
   case X86II::MRMSrcMemFSIB:
     // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

@@ -1051,7 +1051,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
 
   bool EncodeRC = false;
   uint8_t EVEX_rc = 0;
-  bool IsND = X86II::isND(TSFlags);
+  bool IsND = X86II::hasNewDataDestination(TSFlags);
 
   unsigned CurOp = X86II::getOperandBias(Desc);
 
@@ -1078,7 +1078,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
     //  MemAddr, src1(ModR/M), imm8
     //
     // NDD:
-    // dst(VEX_4V), MemAddr, src1(ModR/M)
+    //  dst(VEX_4V), MemAddr, src1(ModR/M)
     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
     Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
@@ -1533,7 +1533,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
 
   unsigned OpcodeOffset = 0;
 
-  bool IsND = X86II::isND(TSFlags);
+  bool IsND = X86II::hasNewDataDestination(TSFlags);
 
   uint64_t Form = TSFlags & X86II::FormMask;
   switch (Form) {

llvm/utils/TableGen/X86RecognizableInstr.h

@@ -172,7 +172,7 @@ enum { PD = 1, XS = 2, XD = 3, PS = 4 };
 enum { VEX = 1, XOP = 2, EVEX = 3 };
 enum { OpSize16 = 1, OpSize32 = 2 };
 enum { AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 };
-enum { ExplicitREX2 = 1, ExplicitVEX = 2, ExplicitEVEX = 3 };
+enum { ExplicitREX2 = 1, ExplicitEVEX = 3 };
 } // namespace X86Local
 
 namespace X86Disassembler {