Revert "ELF: Add branch-to-branch optimization."

zmodem · zmodem · commit 1e95349dbe32 · 2025-06-23T13:26:02.000+02:00
This caused assertion failures in applyBranchToBranchOpt(): llvm/include/llvm/Support/Casting.h:578: decltype(auto) llvm::cast(From*) [with To = lld::elf::InputSection; From = lld::elf::InputSectionBase]: Assertion `isa<To>(Val) && "cast<Ty>() argument of incompatible type!"' failed. See comment on the PR (#138366) This reverts commit 491b82a. This also reverts the follow-up "[lld] Use llvm::partition_point (NFC) (#145209)" This reverts commit 2ac293f.
diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp
@@ -11,7 +11,6 @@
 #include "Symbols.h"
 #include "SyntheticSections.h"
 #include "Target.h"
-#include "TargetImpl.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/Support/Endian.h"
 
@@ -83,7 +82,6 @@ class AArch64 : public TargetInfo {
                 uint64_t val) const override;
   RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override;
   void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override;
-  void applyBranchToBranchOpt() const override;
 
 private:
   void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
@@ -976,62 +974,6 @@ void AArch64::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
   }
 }
 
-static std::optional<uint64_t> getControlTransferAddend(InputSection &is,
-                                                        Relocation &r) {
-  // Identify a control transfer relocation for the branch-to-branch
-  // optimization. A "control transfer relocation" means a B or BL
-  // target but it also includes relative vtable relocations for example.
-  //
-  // We require the relocation type to be JUMP26, CALL26 or PLT32. With a
-  // relocation type of PLT32 the value may be assumed to be used for branching
-  // directly to the symbol and the addend is only used to produce the relocated
-  // value (hence the effective addend is always 0). This is because if a PLT is
-  // needed the addend will be added to the address of the PLT, and it doesn't
-  // make sense to branch into the middle of a PLT. For example, relative vtable
-  // relocations use PLT32 and 0 or a positive value as the addend but still are
-  // used to branch to the symbol.
-  //
-  // With JUMP26 or CALL26 the only reasonable interpretation of a non-zero
-  // addend is that we are branching to symbol+addend so that becomes the
-  // effective addend.
-  if (r.type == R_AARCH64_PLT32)
-    return 0;
-  if (r.type == R_AARCH64_JUMP26 || r.type == R_AARCH64_CALL26)
-    return r.addend;
-  return std::nullopt;
-}
-
-static std::pair<Relocation *, uint64_t>
-getBranchInfoAtTarget(InputSection &is, uint64_t offset) {
-  auto *i = llvm::partition_point(
-      is.relocations, [&](Relocation &r) { return r.offset < offset; });
-  if (i != is.relocations.end() && i->offset == offset &&
-      i->type == R_AARCH64_JUMP26) {
-    return {i, i->addend};
-  }
-  return {nullptr, 0};
-}
-
-static void redirectControlTransferRelocations(Relocation &r1,
-                                               const Relocation &r2) {
-  r1.expr = r2.expr;
-  r1.sym = r2.sym;
-  // With PLT32 we must respect the original addend as that affects the value's
-  // interpretation. With the other relocation types the original addend is
-  // irrelevant because it referred to an offset within the original target
-  // section so we overwrite it.
-  if (r1.type == R_AARCH64_PLT32)
-    r1.addend += r2.addend;
-  else
-    r1.addend = r2.addend;
-}
-
-void AArch64::applyBranchToBranchOpt() const {
-  applyBranchToBranchOptImpl(ctx, getControlTransferAddend,
-                             getBranchInfoAtTarget,
-                             redirectControlTransferRelocations);
-}
-
 // AArch64 may use security features in variant PLT sequences. These are:
 // Pointer Authentication (PAC), introduced in armv8.3-a and Branch Target
 // Indicator (BTI) introduced in armv8.5-a. The additional instructions used
diff --git a/lld/ELF/Arch/TargetImpl.h b/lld/ELF/Arch/TargetImpl.h
diff --git a/lld/ELF/Arch/X86_64.cpp b/lld/ELF/Arch/X86_64.cpp
@@ -11,7 +11,6 @@
 #include "Symbols.h"
 #include "SyntheticSections.h"
 #include "Target.h"
-#include "TargetImpl.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/MathExtras.h"
@@ -50,7 +49,6 @@ class X86_64 : public TargetInfo {
   bool deleteFallThruJmpInsn(InputSection &is, InputFile *file,
                              InputSection *nextIS) const override;
   bool relaxOnce(int pass) const override;
-  void applyBranchToBranchOpt() const override;
 
 private:
   void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
@@ -1163,72 +1161,6 @@ void X86_64::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
   }
 }
 
-static std::optional<uint64_t> getControlTransferAddend(InputSection &is,
-                                                        Relocation &r) {
-  // Identify a control transfer relocation for the branch-to-branch
-  // optimization. A "control transfer relocation" usually means a CALL or JMP
-  // target but it also includes relative vtable relocations for example.
-  //
-  // We require the relocation type to be PLT32. With a relocation type of PLT32
-  // the value may be assumed to be used for branching directly to the symbol
-  // and the addend is only used to produce the relocated value (hence the
-  // effective addend is always 0). This is because if a PLT is needed the
-  // addend will be added to the address of the PLT, and it doesn't make sense
-  // to branch into the middle of a PLT. For example, relative vtable
-  // relocations use PLT32 and 0 or a positive value as the addend but still are
-  // used to branch to the symbol.
-  //
-  // STT_SECTION symbols are a special case on x86 because the LLVM assembler
-  // uses them for branches to local symbols which are assembled as referring to
-  // the section symbol with the addend equal to the symbol value - 4.
-  if (r.type == R_X86_64_PLT32) {
-    if (r.sym->isSection())
-      return r.addend + 4;
-    return 0;
-  }
-  return std::nullopt;
-}
-
-static std::pair<Relocation *, uint64_t>
-getBranchInfoAtTarget(InputSection &is, uint64_t offset) {
-  auto content = is.contentMaybeDecompress();
-  if (content.size() > offset && content[offset] == 0xe9) { // JMP immediate
-    auto *i = llvm::partition_point(
-        is.relocations, [&](Relocation &r) { return r.offset < offset + 1; });
-    // Unlike with getControlTransferAddend() it is valid to accept a PC32
-    // relocation here because we know that this is actually a JMP and not some
-    // other reference, so the interpretation is that we add 4 to the addend and
-    // use that as the effective addend.
-    if (i != is.relocations.end() && i->offset == offset + 1 &&
-        (i->type == R_X86_64_PC32 || i->type == R_X86_64_PLT32)) {
-      return {i, i->addend + 4};
-    }
-  }
-  return {nullptr, 0};
-}
-
-static void redirectControlTransferRelocations(Relocation &r1,
-                                               const Relocation &r2) {
-  // The isSection() check handles the STT_SECTION case described above.
-  // In that case the original addend is irrelevant because it referred to an
-  // offset within the original target section so we overwrite it.
-  //
-  // The +4 is here to compensate for r2.addend which will likely be -4,
-  // but may also be addend-4 in case of a PC32 branch to symbol+addend.
-  if (r1.sym->isSection())
-    r1.addend = r2.addend;
-  else
-    r1.addend += r2.addend + 4;
-  r1.expr = r2.expr;
-  r1.sym = r2.sym;
-}
-
-void X86_64::applyBranchToBranchOpt() const {
-  applyBranchToBranchOptImpl(ctx, getControlTransferAddend,
-                             getBranchInfoAtTarget,
-                             redirectControlTransferRelocations);
-}
-
 // If Intel Indirect Branch Tracking is enabled, we have to emit special PLT
 // entries containing endbr64 instructions. A PLT entry will be split into two
 // parts, one in .plt.sec (writePlt), and the other in .plt (writeIBTPlt).
diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h
@@ -302,7 +302,6 @@ struct Config {
   bool bpFunctionOrderForCompression = false;
   bool bpDataOrderForCompression = false;
   bool bpVerboseSectionOrderer = false;
-  bool branchToBranch = false;
   bool checkSections;
   bool checkDynamicRelocs;
   std::optional<llvm::DebugCompressionType> compressDebugSections;
diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp
@@ -1644,8 +1644,6 @@ static void readConfigs(Ctx &ctx, opt::InputArgList &args) {
   ctx.arg.zWxneeded = hasZOption(args, "wxneeded");
   setUnresolvedSymbolPolicy(ctx, args);
   ctx.arg.power10Stubs = args.getLastArgValue(OPT_power10_stubs_eq) != "no";
-  ctx.arg.branchToBranch = args.hasFlag(
-      OPT_branch_to_branch, OPT_no_branch_to_branch, ctx.arg.optimize >= 2);
 
   if (opt::Arg *arg = args.getLastArg(OPT_eb, OPT_el)) {
     if (arg->getOption().matches(OPT_eb))
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
@@ -430,9 +430,8 @@ InputSectionBase *InputSection::getRelocatedSection() const {
 
 template <class ELFT, class RelTy>
 void InputSection::copyRelocations(Ctx &ctx, uint8_t *buf) {
-  bool linkerRelax =
-      ctx.arg.relax && is_contained({EM_RISCV, EM_LOONGARCH}, ctx.arg.emachine);
-  if (!ctx.arg.relocatable && (linkerRelax || ctx.arg.branchToBranch)) {
+  if (ctx.arg.relax && !ctx.arg.relocatable &&
+      (ctx.arg.emachine == EM_RISCV || ctx.arg.emachine == EM_LOONGARCH)) {
     // On LoongArch and RISC-V, relaxation might change relocations: copy
     // from internal ones that are updated by relaxation.
     InputSectionBase *sec = getRelocatedSection();
diff --git a/lld/ELF/Options.td b/lld/ELF/Options.td
@@ -59,10 +59,6 @@ def build_id: J<"build-id=">, HelpText<"Generate build ID note">,
   MetaVarName<"[fast,md5,sha1,uuid,0x<hexstring>]">;
 def : F<"build-id">, Alias<build_id>, AliasArgs<["sha1"]>, HelpText<"Alias for --build-id=sha1">;
 
-defm branch_to_branch: BB<"branch-to-branch",
-    "Enable branch-to-branch optimization (default at -O2)",
-    "Disable branch-to-branch optimization (default at -O0 and -O1)">;
-
 defm check_sections: B<"check-sections",
     "Check section addresses for overlaps (default)",
     "Do not check section addresses for overlaps">;
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
@@ -1665,10 +1665,9 @@ void RelocationScanner::scan(Relocs<RelTy> rels) {
   }
 
   // Sort relocations by offset for more efficient searching for
-  // R_RISCV_PCREL_HI20, R_PPC64_ADDR64 and the branch-to-branch optimization.
+  // R_RISCV_PCREL_HI20 and R_PPC64_ADDR64.
   if (ctx.arg.emachine == EM_RISCV ||
-      (ctx.arg.emachine == EM_PPC64 && sec->name == ".toc") ||
-      ctx.arg.branchToBranch)
+      (ctx.arg.emachine == EM_PPC64 && sec->name == ".toc"))
     llvm::stable_sort(sec->relocs(),
                       [](const Relocation &lhs, const Relocation &rhs) {
                         return lhs.offset < rhs.offset;
@@ -1959,9 +1958,6 @@ void elf::postScanRelocations(Ctx &ctx) {
   for (ELFFileBase *file : ctx.objectFiles)
     for (Symbol *sym : file->getLocalSymbols())
       fn(*sym);
-
-  if (ctx.arg.branchToBranch)
-    ctx.target->applyBranchToBranchOpt();
 }
 
 static bool mergeCmp(const InputSection *a, const InputSection *b) {
diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h
@@ -101,7 +101,6 @@ class TargetInfo {
 
   virtual void applyJumpInstrMod(uint8_t *loc, JumpModType type,
                                  JumpModType val) const {}
-  virtual void applyBranchToBranchOpt() const {}
 
   virtual ~TargetInfo();
 
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
@@ -62,10 +62,6 @@ ELF Improvements
   on executable sections.
   (`#128883 <https://github.com/llvm/llvm-project/pull/128883>`_)
 
-* For AArch64 and X86_64, added ``--branch-to-branch``, which rewrites branches
-  that point to another branch instruction to instead branch directly to the
-  target of the second instruction. Enabled by default at ``-O2``.
-  
 Breaking changes
 ----------------
 * Executable-only and readable-executable sections are now allowed to be placed
diff --git a/lld/docs/ld.lld.1 b/lld/docs/ld.lld.1
@@ -93,11 +93,6 @@ Bind default visibility defined STB_GLOBAL function symbols locally for
 .Fl shared.
 .It Fl -be8
 Write a Big Endian ELF File using BE8 format(AArch32 only)
-.It Fl -branch-to-branch
-Enable the branch-to-branch optimizations: a branch whose target is
-another branch instruction is rewritten to point to the latter branch
-target (AArch64 and X86_64 only). Enabled by default at
-.Fl O2 Ns .
 .It Fl -build-id Ns = Ns Ar value
 Generate a build ID note.
 .Ar value
@@ -419,7 +414,7 @@ If not specified,
 .Dv a.out
 is used as a default.
 .It Fl O Ns Ar value
-Optimize output file.
+Optimize output file size.
 .Ar value
 may be:
 .Pp
@@ -429,7 +424,7 @@ Disable string merging.
 .It Cm 1
 Enable string merging.
 .It Cm 2
-Enable string tail merging and branch-to-branch optimization.
+Enable string tail merging.
 .El
 .Pp
 .Fl O Ns Cm 1
diff --git a/lld/test/ELF/aarch64-branch-to-branch.s b/lld/test/ELF/aarch64-branch-to-branch.s
diff --git a/lld/test/ELF/x86-64-branch-to-branch.s b/lld/test/ELF/x86-64-branch-to-branch.s
