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Commit 1ed6256

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author
Thorsten Schütt
committed
add splat vector
1 parent bfbbb2e commit 1ed6256

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2 files changed

+22
-1
lines changed

2 files changed

+22
-1
lines changed

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,11 @@ KnownBits GISelKnownBits::getKnownBits(MachineInstr &MI) {
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KnownBits GISelKnownBits::getKnownBits(Register R) {
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const LLT Ty = MRI.getType(R);
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// Since the number of lanes in a scalable vector is unknown at compile time,
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// we track one bit which is implicitly broadcast to all lanes. This means
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// that all lanes in a scalable vector are considered demanded.
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APInt DemandedElts =
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Ty.isVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1);
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Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1);
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return getKnownBits(R, DemandedElts);
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}
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llvm/test/CodeGen/AArch64/GlobalISel/combine-with-flags.mir

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,3 +271,21 @@ body: |
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%z:_(<2 x s32>) = G_ZEXT %t
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$d0 = COPY %z
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...
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---
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name: zext_trunc_nuw_scalable_vector
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: zext_trunc_nuw_scalable_vector
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK-NEXT: %sv0:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[COPY]](s64)
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; CHECK-NEXT: $z0 = COPY %sv0(<vscale x 2 x s64>)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%sv0:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %0:_(s64)
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%t:_(<vscale x 2 x s32>) = nuw G_TRUNC %sv0
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%z:_(<vscale x 2 x s64>) = G_ZEXT %t
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$z0 = COPY %z
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...

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