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[VP] IR expansion for maxnum/minnum
Add basic handling for VP ops that can expand to non-predicate ops Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D159494
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‎llvm/lib/CodeGen/ExpandVectorPredication.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,16 @@ Value *CachingVPExpander::expandPredicationToFPCall(
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replaceOperation(*NewOp, VPI);
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return NewOp;
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}
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case Intrinsic::maxnum:
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case Intrinsic::minnum: {
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Value *Op0 = VPI.getOperand(0);
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Value *Op1 = VPI.getOperand(1);
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Function *Fn = Intrinsic::getDeclaration(
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VPI.getModule(), UnpredicatedIntrinsicID, {VPI.getType()});
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Value *NewOp = Builder.CreateCall(Fn, {Op0, Op1}, VPI.getName());
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replaceOperation(*NewOp, VPI);
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return NewOp;
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}
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case Intrinsic::experimental_constrained_fma:
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case Intrinsic::experimental_constrained_fmuladd: {
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Value *Op0 = VPI.getOperand(0);
@@ -708,6 +718,10 @@ Value *CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
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return expandPredicationToFPCall(Builder, VPI, Intrinsic::fabs);
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case Intrinsic::vp_sqrt:
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return expandPredicationToFPCall(Builder, VPI, Intrinsic::sqrt);
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case Intrinsic::vp_maxnum:
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return expandPredicationToFPCall(Builder, VPI, Intrinsic::maxnum);
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case Intrinsic::vp_minnum:
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return expandPredicationToFPCall(Builder, VPI, Intrinsic::minnum);
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case Intrinsic::vp_load:
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case Intrinsic::vp_store:
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case Intrinsic::vp_gather:

‎llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -404,3 +404,162 @@ define void @vp_fmuladd_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i4 %a5
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}
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declare <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>, <4 x i1>, i32)
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declare <4 x float> @llvm.vp.maxnum.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
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define <4 x float> @vfmax_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {
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; SSE-LABEL: vfmax_vv_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: maxps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: vfmax_vv_v4f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vmaxps %xmm0, %xmm1, %xmm2
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; AVX1-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: vfmax_vv_v4f32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmaxps %xmm0, %xmm1, %xmm2
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; AVX2-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: vfmax_vv_v4f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vmaxps %xmm0, %xmm1, %xmm2
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; AVX512-NEXT: vcmpunordps %xmm0, %xmm0, %k1
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; AVX512-NEXT: vmovaps %xmm1, %xmm2 {%k1}
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; AVX512-NEXT: vmovaps %xmm2, %xmm0
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; AVX512-NEXT: retq
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%v = call <4 x float> @llvm.vp.maxnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)
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ret <4 x float> %v
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}
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declare <8 x float> @llvm.vp.maxnum.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
445+
define <8 x float> @vfmax_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {
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; SSE-LABEL: vfmax_vv_v8f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm2, %xmm4
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; SSE-NEXT: maxps %xmm0, %xmm4
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: andnps %xmm4, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: movaps %xmm3, %xmm2
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; SSE-NEXT: maxps %xmm1, %xmm2
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; SSE-NEXT: cmpunordps %xmm1, %xmm1
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: andnps %xmm2, %xmm1
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; SSE-NEXT: orps %xmm3, %xmm1
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; SSE-NEXT: retq
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;
462+
; AVX1-LABEL: vfmax_vv_v8f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vmaxps %ymm0, %ymm1, %ymm2
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; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
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; AVX1-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: vfmax_vv_v8f32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmaxps %ymm0, %ymm1, %ymm2
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; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
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; AVX2-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: vfmax_vv_v8f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vmaxps %ymm0, %ymm1, %ymm2
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; AVX512-NEXT: vcmpunordps %ymm0, %ymm0, %k1
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; AVX512-NEXT: vmovaps %ymm1, %ymm2 {%k1}
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; AVX512-NEXT: vmovaps %ymm2, %ymm0
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; AVX512-NEXT: retq
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%v = call <8 x float> @llvm.vp.maxnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)
484+
ret <8 x float> %v
485+
}
486+
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declare <4 x float> @llvm.vp.minnum.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
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define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {
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; SSE-LABEL: vfmin_vv_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: minps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: vfmin_vv_v4f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vminps %xmm0, %xmm1, %xmm2
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; AVX1-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: vfmin_vv_v4f32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vminps %xmm0, %xmm1, %xmm2
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; AVX2-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: vfmin_vv_v4f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vminps %xmm0, %xmm1, %xmm2
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; AVX512-NEXT: vcmpunordps %xmm0, %xmm0, %k1
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; AVX512-NEXT: vmovaps %xmm1, %xmm2 {%k1}
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; AVX512-NEXT: vmovaps %xmm2, %xmm0
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; AVX512-NEXT: retq
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%v = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)
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ret <4 x float> %v
522+
}
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declare <8 x float> @llvm.vp.minnum.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
525+
define <8 x float> @vfmin_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {
526+
; SSE-LABEL: vfmin_vv_v8f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm2, %xmm4
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; SSE-NEXT: minps %xmm0, %xmm4
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm2
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; SSE-NEXT: andnps %xmm4, %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: movaps %xmm3, %xmm2
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; SSE-NEXT: minps %xmm1, %xmm2
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; SSE-NEXT: cmpunordps %xmm1, %xmm1
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: andnps %xmm2, %xmm1
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; SSE-NEXT: orps %xmm3, %xmm1
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; SSE-NEXT: retq
541+
;
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; AVX1-LABEL: vfmin_vv_v8f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vminps %ymm0, %ymm1, %ymm2
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; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
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; AVX1-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: vfmin_vv_v8f32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vminps %ymm0, %ymm1, %ymm2
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; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
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; AVX2-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: vfmin_vv_v8f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vminps %ymm0, %ymm1, %ymm2
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; AVX512-NEXT: vcmpunordps %ymm0, %ymm0, %k1
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; AVX512-NEXT: vmovaps %ymm1, %ymm2 {%k1}
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; AVX512-NEXT: vmovaps %ymm2, %ymm0
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; AVX512-NEXT: retq
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%v = call <8 x float> @llvm.vp.minnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)
564+
ret <8 x float> %v
565+
}

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