@@ -50993,7 +50993,8 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
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}
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// Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))
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- static SDValue canonicalizeBitSelect(SDNode *N, SelectionDAG &DAG,
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+ static SDValue canonicalizeBitSelect(SDNode *N, const SDLoc &DL,
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+ SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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assert(N->getOpcode() == ISD::OR && "Unexpected Opcode");
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@@ -51033,8 +51034,6 @@ static SDValue canonicalizeBitSelect(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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- SDLoc DL(N);
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-
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if (useVPTERNLOG(Subtarget, VT)) {
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// Emit a VPTERNLOG node directly - 0xCA is the imm code for A?B:C.
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// VPTERNLOG is only available as vXi32/64-bit types.
@@ -51097,7 +51096,8 @@ static bool matchLogicBlend(SDNode *N, SDValue &X, SDValue &Y, SDValue &Mask) {
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// (or (and (m, (sub 0, x)), (pandn m, x)))
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// into:
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// (sub (xor X, M), M)
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- static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG,
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+ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, const SDLoc &DL,
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+ SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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assert(N->getOpcode() == ISD::OR && "Unexpected Opcode");
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@@ -51122,8 +51122,6 @@ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG,
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if (!MaskVT.isInteger() || DAG.ComputeNumSignBits(Mask) != EltBits)
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return SDValue();
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- SDLoc DL(N);
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-
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// Attempt to combine to conditional negate: (sub (xor X, M), M)
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if (SDValue Res = combineLogicBlendIntoConditionalNegate(VT, Mask, X, Y, DL,
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DAG, Subtarget))
@@ -51607,10 +51605,10 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
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if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
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return R;
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- if (SDValue R = canonicalizeBitSelect(N, DAG, Subtarget))
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+ if (SDValue R = canonicalizeBitSelect(N, dl, DAG, Subtarget))
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return R;
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- if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget))
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+ if (SDValue R = combineLogicBlendIntoPBLENDV(N, dl, DAG, Subtarget))
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return R;
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// (0 - SetCC) | C -> (zext (not SetCC)) * (C + 1) - 1 if we can get a LEA out of it.
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