[RISCV] Add MC support for zicldst

Author: dtcxzyw

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -130,6 +130,13 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
                       AssemblerPredicate<(all_of FeatureStdExtZicond),
                           "'Zicond' (Integer Conditional Operations)">;
 
+def FeatureStdExtZicldst
+    : RISCVExtension<"zicldst", 1, 0,
+                     "'Zicldst' (Integer Conditional Load Store)">;
+def HasStdExtZicldst : Predicate<"Subtarget->hasStdExtZicldst()">,
+                      AssemblerPredicate<(all_of FeatureStdExtZicldst),
+                          "'Zicldst' (Integer Conditional Load Store)">;
+
 def FeatureStdExtZifencei
     : RISCVExtension<"zifencei", 2, 0,
                      "'Zifencei' (fence.i)">;

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2068,6 +2068,7 @@ include "RISCVInstrInfoZcmop.td"
 include "RISCVInstrInfoZimop.td"
 include "RISCVInstrInfoZicbo.td"
 include "RISCVInstrInfoZicond.td"
+include "RISCVInstrInfoZicldst.td"
 include "RISCVInstrInfoZicfiss.td"
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfoZicldst.td

@@ -0,0 +1,47 @@
+//===-- RISCVInstrInfoZicldst.td ---------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard Integer
+// Conditional Load Store operations extension (Zicldst).
+//
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+class CondLoad_ri<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd), (ins GPRMem:$rs1, simm12:$imm12),
+              opcodestr, "$rd, ${imm12}(${rs1})">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+class CondStore_rri<bits<3> funct3, string opcodestr>
+    : RVInstS<funct3, OPC_CUSTOM_1, (outs),
+              (ins GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
+              opcodestr, "$rs2, ${imm12}(${rs1})">;
+}
+
+let Predicates = [HasStdExtZicldst] in {
+
+let IsSignExtendingOpW = 1 in {
+def CLB  : CondLoad_ri<0b000, "clb">, Sched<[WriteLDB, ReadMemBase]>;
+def CLH  : CondLoad_ri<0b001, "clh">, Sched<[WriteLDH, ReadMemBase]>;
+def CLW  : CondLoad_ri<0b010, "clw">, Sched<[WriteLDW, ReadMemBase]>;
+def CLBU : CondLoad_ri<0b100, "clbu">, Sched<[WriteLDB, ReadMemBase]>;
+def CLHU : CondLoad_ri<0b101, "clhu">, Sched<[WriteLDH, ReadMemBase]>;
+}
+
+def CSB : CondStore_rri<0b000, "csb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
+def CSH : CondStore_rri<0b001, "csh">, Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
+def CSW : CondStore_rri<0b010, "csw">, Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+
+} // Predicates = [HasStdExtZcildst]
+
+let Predicates = [HasStdExtZicldst, IsRV64] in {
+def CLWU   : CondLoad_ri<0b110, "clwu">, Sched<[WriteLDW, ReadMemBase]>;
+def CLD    : CondLoad_ri<0b011, "cld">, Sched<[WriteLDD, ReadMemBase]>;
+def CSD    : CondStore_rri<0b011, "csd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
+} // Predicates = [HasStdExtZicldst, IsRV64]

llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

@@ -879,6 +879,7 @@ R"(All available -march extensions for RISC-V
     ziccif               1.0
     zicclsm              1.0
     ziccrse              1.0
+    zicldst              1.0
     zicntr               2.0
     zicond               1.0
     zicsr                2.0