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davemgreendavemgreen
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[ARM] Add neon vector support for trunc
As per #142559, this marks ftrunc as legal for Neon and upgrades the existing arm.neon.vrintz intrinsics.
1 parent 6553753 commit 1f8f477

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8 files changed

+16
-60
lines changed

8 files changed

+16
-60
lines changed

‎clang/lib/CodeGen/TargetBuiltins/ARM.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -838,7 +838,7 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
838838
NEONMAP1(vrecpsq_v, arm_neon_vrecps, Add1ArgType),
839839
NEONMAP2(vrhadd_v, arm_neon_vrhaddu, arm_neon_vrhadds, Add1ArgType | UnsignedAlts),
840840
NEONMAP2(vrhaddq_v, arm_neon_vrhaddu, arm_neon_vrhadds, Add1ArgType | UnsignedAlts),
841-
NEONMAP1(vrnd_v, arm_neon_vrintz, Add1ArgType),
841+
NEONMAP1(vrnd_v, trunc, Add1ArgType),
842842
NEONMAP1(vrnda_v, round, Add1ArgType),
843843
NEONMAP1(vrndaq_v, round, Add1ArgType),
844844
NEONMAP0(vrndi_v),
@@ -849,7 +849,7 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
849849
NEONMAP1(vrndnq_v, arm_neon_vrintn, Add1ArgType),
850850
NEONMAP1(vrndp_v, ceil, Add1ArgType),
851851
NEONMAP1(vrndpq_v, ceil, Add1ArgType),
852-
NEONMAP1(vrndq_v, arm_neon_vrintz, Add1ArgType),
852+
NEONMAP1(vrndq_v, trunc, Add1ArgType),
853853
NEONMAP1(vrndx_v, arm_neon_vrintx, Add1ArgType),
854854
NEONMAP1(vrndxq_v, arm_neon_vrintx, Add1ArgType),
855855
NEONMAP2(vrshl_v, arm_neon_vrshiftu, arm_neon_vrshifts, Add1ArgType | UnsignedAlts),

‎clang/test/CodeGen/arm-neon-directed-rounding.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -266,7 +266,7 @@ float32x4_t test_vrndxq_f32(float32x4_t a) {
266266
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
267267
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
268268
// CHECK-A32-NEXT: [[VRND_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
269-
// CHECK-A32-NEXT: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintz.v2f32(<2 x float> [[VRND_V_I]])
269+
// CHECK-A32-NEXT: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.trunc.v2f32(<2 x float> [[VRND_V_I]])
270270
// CHECK-A32-NEXT: [[VRND_V2_I:%.*]] = bitcast <2 x float> [[VRND_V1_I]] to <8 x i8>
271271
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND_V2_I]] to <2 x i32>
272272
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
@@ -291,7 +291,7 @@ float32x2_t test_vrnd_f32(float32x2_t a) {
291291
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
292292
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
293293
// CHECK-A32-NEXT: [[VRNDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
294-
// CHECK-A32-NEXT: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintz.v4f32(<4 x float> [[VRNDQ_V_I]])
294+
// CHECK-A32-NEXT: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> [[VRNDQ_V_I]])
295295
// CHECK-A32-NEXT: [[VRNDQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDQ_V1_I]] to <16 x i8>
296296
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDQ_V2_I]] to <4 x i32>
297297
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>

‎clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -522,7 +522,7 @@ float16x8_t test_vrecpeq_f16(float16x8_t a) {
522522
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
523523
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
524524
// CHECK-NEXT: [[VRND_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
525-
// CHECK-NEXT: [[VRND_V1_I:%.*]] = call <4 x half> @llvm.arm.neon.vrintz.v4f16(<4 x half> [[VRND_V_I]])
525+
// CHECK-NEXT: [[VRND_V1_I:%.*]] = call <4 x half> @llvm.trunc.v4f16(<4 x half> [[VRND_V_I]])
526526
// CHECK-NEXT: [[VRND_V2_I:%.*]] = bitcast <4 x half> [[VRND_V1_I]] to <8 x i8>
527527
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND_V2_I]] to <4 x i16>
528528
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>
@@ -538,7 +538,7 @@ float16x4_t test_vrnd_f16(float16x4_t a) {
538538
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
539539
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
540540
// CHECK-NEXT: [[VRNDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
541-
// CHECK-NEXT: [[VRNDQ_V1_I:%.*]] = call <8 x half> @llvm.arm.neon.vrintz.v8f16(<8 x half> [[VRNDQ_V_I]])
541+
// CHECK-NEXT: [[VRNDQ_V1_I:%.*]] = call <8 x half> @llvm.trunc.v8f16(<8 x half> [[VRNDQ_V_I]])
542542
// CHECK-NEXT: [[VRNDQ_V2_I:%.*]] = bitcast <8 x half> [[VRNDQ_V1_I]] to <16 x i8>
543543
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDQ_V2_I]] to <8 x i16>
544544
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half>

‎llvm/include/llvm/IR/IntrinsicsARM.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,6 @@ def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
680680
// Vector and Scalar Rounding.
681681
def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
682682
def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
683-
def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
684683

685684
// De-interleaving vector loads from N-element structures.
686685
// Source operands are the address and alignment.

‎llvm/lib/IR/AutoUpgrade.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -722,6 +722,7 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F,
722722
.StartsWith("vrinta.", Intrinsic::round)
723723
.StartsWith("vrintm.", Intrinsic::floor)
724724
.StartsWith("vrintp.", Intrinsic::ceil)
725+
.StartsWith("vrintz", Intrinsic::trunc)
725726
.Default(Intrinsic::not_intrinsic);
726727
if (ID != Intrinsic::not_intrinsic) {
727728
NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID,

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1550,6 +1550,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15501550
setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
15511551
setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
15521552
setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1553+
setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
1554+
setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
15531555
}
15541556

15551557
if (Subtarget->hasFullFP16()) {
@@ -1569,6 +1571,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15691571
setOperationAction(ISD::FROUND, MVT::v8f16, Legal);
15701572
setOperationAction(ISD::FCEIL, MVT::v4f16, Legal);
15711573
setOperationAction(ISD::FCEIL, MVT::v8f16, Legal);
1574+
setOperationAction(ISD::FTRUNC, MVT::v4f16, Legal);
1575+
setOperationAction(ISD::FTRUNC, MVT::v8f16, Legal);
15721576
}
15731577
}
15741578

‎llvm/lib/Target/ARM/ARMInstrNEON.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7315,7 +7315,7 @@ multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
73157315
defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
73167316
defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
73177317
defm VRINTAN : VRINT_FPI<"a", 0b010, fround>;
7318-
defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
7318+
defm VRINTZN : VRINT_FPI<"z", 0b011, ftrunc>;
73197319
defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;
73207320
defm VRINTPN : VRINT_FPI<"p", 0b111, fceil>;
73217321

‎llvm/test/CodeGen/ARM/vrint.ll

Lines changed: 4 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -2137,21 +2137,7 @@ define <4 x half> @frintz_4h(<4 x half> %A) nounwind {
21372137
;
21382138
; CHECK-FP16-LABEL: frintz_4h:
21392139
; CHECK-FP16: @ %bb.0:
2140-
; CHECK-FP16-NEXT: vmovx.f16 s2, s0
2141-
; CHECK-FP16-NEXT: vrintz.f16 s2, s2
2142-
; CHECK-FP16-NEXT: vmov r0, s2
2143-
; CHECK-FP16-NEXT: vrintz.f16 s2, s0
2144-
; CHECK-FP16-NEXT: vmov r1, s2
2145-
; CHECK-FP16-NEXT: vrintz.f16 s2, s1
2146-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
2147-
; CHECK-FP16-NEXT: vrintz.f16 s0, s0
2148-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
2149-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
2150-
; CHECK-FP16-NEXT: vmov r0, s2
2151-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
2152-
; CHECK-FP16-NEXT: vmov r0, s0
2153-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
2154-
; CHECK-FP16-NEXT: vorr d0, d16, d16
2140+
; CHECK-FP16-NEXT: vrintz.f16 d0, d0
21552141
; CHECK-FP16-NEXT: bx lr
21562142
%tmp3 = call <4 x half> @llvm.trunc.v4f16(<4 x half> %A)
21572143
ret <4 x half> %tmp3
@@ -2301,35 +2287,7 @@ define <8 x half> @frintz_8h(<8 x half> %A) nounwind {
23012287
;
23022288
; CHECK-FP16-LABEL: frintz_8h:
23032289
; CHECK-FP16: @ %bb.0:
2304-
; CHECK-FP16-NEXT: vmovx.f16 s4, s2
2305-
; CHECK-FP16-NEXT: vrintz.f16 s4, s4
2306-
; CHECK-FP16-NEXT: vmov r0, s4
2307-
; CHECK-FP16-NEXT: vrintz.f16 s4, s2
2308-
; CHECK-FP16-NEXT: vmov r1, s4
2309-
; CHECK-FP16-NEXT: vrintz.f16 s4, s3
2310-
; CHECK-FP16-NEXT: vmov.16 d17[0], r1
2311-
; CHECK-FP16-NEXT: vmov.16 d17[1], r0
2312-
; CHECK-FP16-NEXT: vmov r0, s4
2313-
; CHECK-FP16-NEXT: vmovx.f16 s4, s3
2314-
; CHECK-FP16-NEXT: vrintz.f16 s4, s4
2315-
; CHECK-FP16-NEXT: vmov.16 d17[2], r0
2316-
; CHECK-FP16-NEXT: vmov r0, s4
2317-
; CHECK-FP16-NEXT: vmovx.f16 s4, s0
2318-
; CHECK-FP16-NEXT: vrintz.f16 s4, s4
2319-
; CHECK-FP16-NEXT: vmov.16 d17[3], r0
2320-
; CHECK-FP16-NEXT: vmov r0, s4
2321-
; CHECK-FP16-NEXT: vrintz.f16 s4, s0
2322-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
2323-
; CHECK-FP16-NEXT: vmov r1, s4
2324-
; CHECK-FP16-NEXT: vrintz.f16 s4, s1
2325-
; CHECK-FP16-NEXT: vrintz.f16 s0, s0
2326-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
2327-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
2328-
; CHECK-FP16-NEXT: vmov r0, s4
2329-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
2330-
; CHECK-FP16-NEXT: vmov r0, s0
2331-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
2332-
; CHECK-FP16-NEXT: vorr q0, q8, q8
2290+
; CHECK-FP16-NEXT: vrintz.f16 q0, q0
23332291
; CHECK-FP16-NEXT: bx lr
23342292
%tmp3 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %A)
23352293
ret <8 x half> %tmp3
@@ -2355,9 +2313,7 @@ define <2 x float> @frintz_2s(<2 x float> %A) nounwind {
23552313
;
23562314
; CHECK-LABEL: frintz_2s:
23572315
; CHECK: @ %bb.0:
2358-
; CHECK-NEXT: vrintz.f32 s3, s1
2359-
; CHECK-NEXT: vrintz.f32 s2, s0
2360-
; CHECK-NEXT: vmov.f64 d0, d1
2316+
; CHECK-NEXT: vrintz.f32 d0, d0
23612317
; CHECK-NEXT: bx lr
23622318
%tmp3 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %A)
23632319
ret <2 x float> %tmp3
@@ -2389,11 +2345,7 @@ define <4 x float> @frintz_4s(<4 x float> %A) nounwind {
23892345
;
23902346
; CHECK-LABEL: frintz_4s:
23912347
; CHECK: @ %bb.0:
2392-
; CHECK-NEXT: vrintz.f32 s7, s3
2393-
; CHECK-NEXT: vrintz.f32 s6, s2
2394-
; CHECK-NEXT: vrintz.f32 s5, s1
2395-
; CHECK-NEXT: vrintz.f32 s4, s0
2396-
; CHECK-NEXT: vorr q0, q1, q1
2348+
; CHECK-NEXT: vrintz.f32 q0, q0
23972349
; CHECK-NEXT: bx lr
23982350
%tmp3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %A)
23992351
ret <4 x float> %tmp3

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