@@ -2411,8 +2411,9 @@ unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) {
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unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {
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if (VT.isRISCVVectorTuple()) {
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unsigned NF = VT.getRISCVVectorTupleNumFields();
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- unsigned RegsPerField = std::max(1U, (unsigned)VT.getSizeInBits() /
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- (NF * RISCV::RVVBitsPerBlock));
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+ unsigned RegsPerField =
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+ std::max(1U, (unsigned)VT.getSizeInBits().getKnownMinValue() /
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+ (NF * RISCV::RVVBitsPerBlock));
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switch (RegsPerField) {
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case 1:
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if (NF == 2)
@@ -7036,7 +7037,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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SDLoc DL(Op);
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MVT XLenVT = Subtarget.getXLenVT();
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unsigned NF = VecTy.getRISCVVectorTupleNumFields();
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- unsigned Sz = VecTy.getSizeInBits();
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+ unsigned Sz = VecTy.getSizeInBits().getKnownMinValue() ;
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unsigned NumElts = Sz / (NF * 8);
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int Log2LMUL = Log2_64(NumElts) - 3;
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@@ -7079,7 +7080,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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SDLoc DL(Op);
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MVT XLenVT = Subtarget.getXLenVT();
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unsigned NF = VecTy.getRISCVVectorTupleNumFields();
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- unsigned Sz = VecTy.getSizeInBits();
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+ unsigned Sz = VecTy.getSizeInBits().getKnownMinValue() ;
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unsigned NumElts = Sz / (NF * 8);
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int Log2LMUL = Log2_64(NumElts) - 3;
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@@ -21372,6 +21373,27 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
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return true;
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}
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+ if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
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+ #ifndef NDEBUG
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+ unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
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+ [[maybe_unused]] unsigned ValLMUL =
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+ divideCeil(ValueVT.getSizeInBits().getKnownMinValue(),
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+ ValNF * RISCV::RVVBitsPerBlock);
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+ unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
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+ [[maybe_unused]] unsigned PartLMUL =
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+ divideCeil(PartVT.getSizeInBits().getKnownMinValue(),
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+ PartNF * RISCV::RVVBitsPerBlock);
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+ assert(ValNF == PartNF && ValLMUL == PartLMUL &&
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+ "RISC-V vector tuple type only accepts same register class type "
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+ "TUPLE_INSERT");
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+ #endif
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+
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+ Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
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+ Val, DAG.getVectorIdxConstant(0, DL));
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+ Parts[0] = Val;
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+ return true;
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+ }
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+
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if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
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LLVMContext &Context = *DAG.getContext();
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EVT ValueEltVT = ValueVT.getVectorElementType();
@@ -21407,22 +21429,6 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
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}
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}
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- if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
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- unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
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- [[maybe_unused]] unsigned ValLMUL =
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- divideCeil(ValueVT.getSizeInBits(), ValNF * RISCV::RVVBitsPerBlock);
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- unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
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- [[maybe_unused]] unsigned PartLMUL =
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- divideCeil(PartVT.getSizeInBits(), PartNF * RISCV::RVVBitsPerBlock);
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- assert(ValNF == PartNF && ValLMUL == PartLMUL &&
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- "RISC-V vector tuple type only accepts same register class type "
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- "TUPLE_INSERT");
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-
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- Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
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- Val, DAG.getVectorIdxConstant(0, DL));
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- Parts[0] = Val;
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- return true;
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- }
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return false;
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}
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