Added test case

Author: mikhailramalho

llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll

@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefixes=NO-ZBA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zba < %s | FileCheck -check-prefixes=ZBA %s
+
+define ptr @g(ptr %0, i32 %1) {
+; NO-ZBA-LABEL: g:
+; NO-ZBA:       # %bb.0:
+; NO-ZBA-NEXT:    slli a2, a1, 1
+; NO-ZBA-NEXT:    add a2, a2, a1
+; NO-ZBA-NEXT:    sllw a1, a2, a1
+; NO-ZBA-NEXT:    li a0, 0
+; NO-ZBA-NEXT:    ret
+;
+; ZBA-LABEL: g:
+; ZBA:       # %bb.0:
+; ZBA-NEXT:    sh1add a2, a1, a1
+; ZBA-NEXT:    sllw a1, a2, a1
+; ZBA-NEXT:    li a0, 0
+; ZBA-NEXT:    ret
+  %3 = mul i32 %1, 3
+  %4 = shl i32 %3, %1
+  %5 = sext i32 %4 to i64
+  %6 = inttoptr i64 %5 to ptr
+  %7 = icmp ugt ptr %0, %6
+  br i1 %7, label %10, label %8
+
+8:                                                ; preds = %2
+  %9 = load i8, ptr null, align 1
+  br label %10
+
+10:                                               ; preds = %8, %2
+  ret ptr null
+}