[LoongArch] Pre-commit tests for vector type llvm.bitreverse. NFC (#118053)

A later commit will optimize this.

Author: zhaoqi5

llvm/test/CodeGen/LoongArch/lasx/bitreverse.ll

@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 -mattr=+lasx --verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+declare <32 x i8> @llvm.bitreverse.v32i8(<32 x i8>)
+
+define <32 x i8> @test_bitreverse_v32i8(<32 x i8> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xvslli.b $xr1, $xr0, 4
+; CHECK-NEXT:    xvsrli.b $xr0, $xr0, 4
+; CHECK-NEXT:    xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT:    xvandi.b $xr1, $xr0, 51
+; CHECK-NEXT:    xvslli.b $xr1, $xr1, 2
+; CHECK-NEXT:    xvsrli.b $xr0, $xr0, 2
+; CHECK-NEXT:    xvandi.b $xr0, $xr0, 51
+; CHECK-NEXT:    xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT:    xvandi.b $xr1, $xr0, 85
+; CHECK-NEXT:    xvslli.b $xr1, $xr1, 1
+; CHECK-NEXT:    xvsrli.b $xr0, $xr0, 1
+; CHECK-NEXT:    xvandi.b $xr0, $xr0, 85
+; CHECK-NEXT:    xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+  %b = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %a)
+  ret <32 x i8> %b
+}
+
+declare <16 x i16> @llvm.bitreverse.v16i16(<16 x i16>)
+
+define <16 x i16> @test_bitreverse_v16i16(<16 x i16> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xvshuf4i.b $xr0, $xr0, 177
+; CHECK-NEXT:    xvsrli.h $xr1, $xr0, 4
+; CHECK-NEXT:    xvrepli.b $xr2, 15
+; CHECK-NEXT:    xvand.v $xr1, $xr1, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvslli.h $xr0, $xr0, 4
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvsrli.h $xr1, $xr0, 2
+; CHECK-NEXT:    xvrepli.b $xr2, 51
+; CHECK-NEXT:    xvand.v $xr1, $xr1, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvslli.h $xr0, $xr0, 2
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvsrli.h $xr1, $xr0, 1
+; CHECK-NEXT:    xvrepli.b $xr2, 85
+; CHECK-NEXT:    xvand.v $xr1, $xr1, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvslli.h $xr0, $xr0, 1
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    ret
+  %b = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a)
+  ret <16 x i16> %b
+}
+
+declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>)
+
+define <8 x i32> @test_bitreverse_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xvshuf4i.b $xr0, $xr0, 27
+; CHECK-NEXT:    xvsrli.w $xr1, $xr0, 4
+; CHECK-NEXT:    xvrepli.b $xr2, 15
+; CHECK-NEXT:    xvand.v $xr1, $xr1, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvslli.w $xr0, $xr0, 4
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvsrli.w $xr1, $xr0, 2
+; CHECK-NEXT:    xvrepli.b $xr2, 51
+; CHECK-NEXT:    xvand.v $xr1, $xr1, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvslli.w $xr0, $xr0, 2
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvsrli.w $xr1, $xr0, 1
+; CHECK-NEXT:    xvrepli.b $xr2, 85
+; CHECK-NEXT:    xvand.v $xr1, $xr1, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvslli.w $xr0, $xr0, 1
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    ret
+  %b = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)
+  ret <8 x i32> %b
+}
+
+declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>)
+
+define <4 x i64> @test_bitreverse_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xvpickve2gr.d $a0, $xr0, 0
+; CHECK-NEXT:    bitrev.d $a0, $a0
+; CHECK-NEXT:    xvinsgr2vr.d $xr1, $a0, 0
+; CHECK-NEXT:    xvpickve2gr.d $a0, $xr0, 1
+; CHECK-NEXT:    bitrev.d $a0, $a0
+; CHECK-NEXT:    xvinsgr2vr.d $xr1, $a0, 1
+; CHECK-NEXT:    xvpickve2gr.d $a0, $xr0, 2
+; CHECK-NEXT:    bitrev.d $a0, $a0
+; CHECK-NEXT:    xvinsgr2vr.d $xr1, $a0, 2
+; CHECK-NEXT:    xvpickve2gr.d $a0, $xr0, 3
+; CHECK-NEXT:    bitrev.d $a0, $a0
+; CHECK-NEXT:    xvinsgr2vr.d $xr1, $a0, 3
+; CHECK-NEXT:    xvori.b $xr0, $xr1, 0
+; CHECK-NEXT:    ret
+  %b = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)
+  ret <4 x i64> %b
+}

llvm/test/CodeGen/LoongArch/lsx/bitreverse.ll

@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx --verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>)
+
+define <16 x i8> @test_bitreverse_v16i8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vslli.b $vr1, $vr0, 4
+; CHECK-NEXT:    vsrli.b $vr0, $vr0, 4
+; CHECK-NEXT:    vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT:    vandi.b $vr1, $vr0, 51
+; CHECK-NEXT:    vslli.b $vr1, $vr1, 2
+; CHECK-NEXT:    vsrli.b $vr0, $vr0, 2
+; CHECK-NEXT:    vandi.b $vr0, $vr0, 51
+; CHECK-NEXT:    vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT:    vandi.b $vr1, $vr0, 85
+; CHECK-NEXT:    vslli.b $vr1, $vr1, 1
+; CHECK-NEXT:    vsrli.b $vr0, $vr0, 1
+; CHECK-NEXT:    vandi.b $vr0, $vr0, 85
+; CHECK-NEXT:    vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+  %b = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %a)
+  ret <16 x i8> %b
+}
+
+declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>)
+
+define <8 x i16> @test_bitreverse_v8i16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vshuf4i.b $vr0, $vr0, 177
+; CHECK-NEXT:    vsrli.h $vr1, $vr0, 4
+; CHECK-NEXT:    vrepli.b $vr2, 15
+; CHECK-NEXT:    vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vslli.h $vr0, $vr0, 4
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vsrli.h $vr1, $vr0, 2
+; CHECK-NEXT:    vrepli.b $vr2, 51
+; CHECK-NEXT:    vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vslli.h $vr0, $vr0, 2
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vsrli.h $vr1, $vr0, 1
+; CHECK-NEXT:    vrepli.b $vr2, 85
+; CHECK-NEXT:    vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vslli.h $vr0, $vr0, 1
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    ret
+  %b = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %a)
+  ret <8 x i16> %b
+}
+
+declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>)
+
+define <4 x i32> @test_bitreverse_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vshuf4i.b $vr0, $vr0, 27
+; CHECK-NEXT:    vsrli.w $vr1, $vr0, 4
+; CHECK-NEXT:    vrepli.b $vr2, 15
+; CHECK-NEXT:    vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vslli.w $vr0, $vr0, 4
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vsrli.w $vr1, $vr0, 2
+; CHECK-NEXT:    vrepli.b $vr2, 51
+; CHECK-NEXT:    vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vslli.w $vr0, $vr0, 2
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vsrli.w $vr1, $vr0, 1
+; CHECK-NEXT:    vrepli.b $vr2, 85
+; CHECK-NEXT:    vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vslli.w $vr0, $vr0, 1
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    ret
+  %b = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %a)
+  ret <4 x i32> %b
+}
+
+declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>)
+
+define <2 x i64> @test_bitreverse_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: test_bitreverse_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpickve2gr.d $a0, $vr0, 0
+; CHECK-NEXT:    bitrev.d $a0, $a0
+; CHECK-NEXT:    vinsgr2vr.d $vr1, $a0, 0
+; CHECK-NEXT:    vpickve2gr.d $a0, $vr0, 1
+; CHECK-NEXT:    bitrev.d $a0, $a0
+; CHECK-NEXT:    vinsgr2vr.d $vr1, $a0, 1
+; CHECK-NEXT:    vori.b $vr0, $vr1, 0
+; CHECK-NEXT:    ret
+  %b = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a)
+  ret <2 x i64> %b
+}