@@ -746,6 +746,7 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
746
746
const VSETVLIInfo &CurInfo) const ;
747
747
bool needVSETVLIPHI (const VSETVLIInfo &Require,
748
748
const MachineBasicBlock &MBB) const ;
749
+ bool mayChangeVL (const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) const ;
749
750
void insertVSETVLI (MachineBasicBlock &MBB, MachineInstr &MI,
750
751
const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo);
751
752
void insertVSETVLI (MachineBasicBlock &MBB,
@@ -859,41 +860,47 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
859
860
return NewInfo;
860
861
}
861
862
863
+ // / Return true if a vsetvli instruction to change from PrevInfo
864
+ // / to Info might change the VL register. If this returns false,
865
+ // / the vsetvli can use the X0, X0 form.
866
+ bool RISCVInsertVSETVLI::mayChangeVL (const VSETVLIInfo &Info,
867
+ const VSETVLIInfo &PrevInfo) const {
868
+ if (!PrevInfo.isValid () || PrevInfo.isUnknown ())
869
+ return true ;
870
+
871
+ // If the AVL is the same and the SEW+LMUL gives the same VLMAX, VL
872
+ // can not change.
873
+ if (Info.hasSameAVL (PrevInfo) && Info.hasSameVLMAX (PrevInfo))
874
+ return false ;
875
+
876
+ // If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
877
+ // it has the same VLMAX we want and the last VL/VTYPE we observed is the
878
+ // same, then VL can not change.
879
+ if (Info.hasSameVLMAX (PrevInfo) && Info.hasAVLReg () &&
880
+ Info.getAVLReg ().isVirtual ()) {
881
+ if (MachineInstr *DefMI = MRI->getVRegDef (Info.getAVLReg ());
882
+ DefMI && isVectorConfigInstr (*DefMI)) {
883
+ VSETVLIInfo DefInfo = getInfoForVSETVLI (*DefMI);
884
+ if (DefInfo.hasSameAVL (PrevInfo) && DefInfo.hasSameVLMAX (PrevInfo))
885
+ return false ;
886
+ }
887
+ }
888
+ return true ;
889
+ }
890
+
862
891
void RISCVInsertVSETVLI::insertVSETVLI (MachineBasicBlock &MBB,
863
892
MachineBasicBlock::iterator InsertPt, DebugLoc DL,
864
893
const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) {
865
894
866
- if (PrevInfo.isValid () && !PrevInfo.isUnknown ()) {
867
- // Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
868
- // VLMAX.
869
- if (Info.hasSameAVL (PrevInfo) && Info.hasSameVLMAX (PrevInfo)) {
870
- BuildMI (MBB, InsertPt, DL, TII->get (RISCV::PseudoVSETVLIX0))
871
- .addReg (RISCV::X0, RegState::Define | RegState::Dead)
872
- .addReg (RISCV::X0, RegState::Kill)
873
- .addImm (Info.encodeVTYPE ())
874
- .addReg (RISCV::VL, RegState::Implicit);
875
- return ;
876
- }
877
-
878
- // If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
879
- // it has the same VLMAX we want and the last VL/VTYPE we observed is the
880
- // same, we can use the X0, X0 form.
881
- if (Info.hasSameVLMAX (PrevInfo) && Info.hasAVLReg () &&
882
- Info.getAVLReg ().isVirtual ()) {
883
- if (MachineInstr *DefMI = MRI->getVRegDef (Info.getAVLReg ())) {
884
- if (isVectorConfigInstr (*DefMI)) {
885
- VSETVLIInfo DefInfo = getInfoForVSETVLI (*DefMI);
886
- if (DefInfo.hasSameAVL (PrevInfo) && DefInfo.hasSameVLMAX (PrevInfo)) {
887
- BuildMI (MBB, InsertPt, DL, TII->get (RISCV::PseudoVSETVLIX0))
888
- .addReg (RISCV::X0, RegState::Define | RegState::Dead)
889
- .addReg (RISCV::X0, RegState::Kill)
890
- .addImm (Info.encodeVTYPE ())
891
- .addReg (RISCV::VL, RegState::Implicit);
892
- return ;
893
- }
894
- }
895
- }
896
- }
895
+ // Use X0, X0 form if VL can't change. Changing only VTYPE is generally
896
+ // cheaper than changing VL.
897
+ if (!mayChangeVL (Info, PrevInfo)) {
898
+ BuildMI (MBB, InsertPt, DL, TII->get (RISCV::PseudoVSETVLIX0))
899
+ .addReg (RISCV::X0, RegState::Define | RegState::Dead)
900
+ .addReg (RISCV::X0, RegState::Kill)
901
+ .addImm (Info.encodeVTYPE ())
902
+ .addReg (RISCV::VL, RegState::Implicit);
903
+ return ;
897
904
}
898
905
899
906
if (Info.hasAVLImm ()) {
0 commit comments