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[RISCV][InsertVSETVLI] Make VL preserving vsetvli emission more explicit [nfc]
This just reorganizes the code to make it clear what the existing cases were doing in common. An upcoming change will extend the logic.
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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 38 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -746,6 +746,7 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
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const VSETVLIInfo &CurInfo) const;
747747
bool needVSETVLIPHI(const VSETVLIInfo &Require,
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const MachineBasicBlock &MBB) const;
749+
bool mayChangeVL(const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) const;
749750
void insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
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const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo);
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void insertVSETVLI(MachineBasicBlock &MBB,
@@ -859,41 +860,47 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
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return NewInfo;
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}
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863+
/// Return true if a vsetvli instruction to change from PrevInfo
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/// to Info might change the VL register. If this returns false,
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/// the vsetvli can use the X0, X0 form.
866+
bool RISCVInsertVSETVLI::mayChangeVL(const VSETVLIInfo &Info,
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const VSETVLIInfo &PrevInfo) const {
868+
if (!PrevInfo.isValid() || PrevInfo.isUnknown())
869+
return true;
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// If the AVL is the same and the SEW+LMUL gives the same VLMAX, VL
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// can not change.
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if (Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo))
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return false;
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// If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
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// it has the same VLMAX we want and the last VL/VTYPE we observed is the
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// same, then VL can not change.
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if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg() &&
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Info.getAVLReg().isVirtual()) {
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if (MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg());
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DefMI && isVectorConfigInstr(*DefMI)) {
883+
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
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if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo))
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return false;
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}
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}
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return true;
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}
890+
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void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertPt, DebugLoc DL,
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const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) {
865894

866-
if (PrevInfo.isValid() && !PrevInfo.isUnknown()) {
867-
// Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
868-
// VLMAX.
869-
if (Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo)) {
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BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
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.addReg(RISCV::X0, RegState::Define | RegState::Dead)
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.addReg(RISCV::X0, RegState::Kill)
873-
.addImm(Info.encodeVTYPE())
874-
.addReg(RISCV::VL, RegState::Implicit);
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return;
876-
}
877-
878-
// If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
879-
// it has the same VLMAX we want and the last VL/VTYPE we observed is the
880-
// same, we can use the X0, X0 form.
881-
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg() &&
882-
Info.getAVLReg().isVirtual()) {
883-
if (MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg())) {
884-
if (isVectorConfigInstr(*DefMI)) {
885-
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
886-
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
887-
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
888-
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
889-
.addReg(RISCV::X0, RegState::Kill)
890-
.addImm(Info.encodeVTYPE())
891-
.addReg(RISCV::VL, RegState::Implicit);
892-
return;
893-
}
894-
}
895-
}
896-
}
895+
// Use X0, X0 form if VL can't change. Changing only VTYPE is generally
896+
// cheaper than changing VL.
897+
if (!mayChangeVL(Info, PrevInfo)) {
898+
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
899+
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
900+
.addReg(RISCV::X0, RegState::Kill)
901+
.addImm(Info.encodeVTYPE())
902+
.addReg(RISCV::VL, RegState::Implicit);
903+
return;
897904
}
898905

899906
if (Info.hasAVLImm()) {

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