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AMDGPU/GlobalISel: Don't mis-select vector index on a constant
Vector indexing with a constant index should be folded out in the legalizer, but this was accidentally falling through. This would produce the indexing operation with $noreg. Handle this case as a dynamic index just in case a bug like this happens again in the future.
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‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

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Original file line numberDiff line numberDiff line change
@@ -1721,6 +1721,12 @@ computeIndirectRegIndex(MachineRegisterInfo &MRI,
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std::tie(IdxBaseReg, Offset, Unused)
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= AMDGPU::getBaseWithConstantOffset(MRI, IdxReg);
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if (IdxBaseReg == AMDGPU::NoRegister) {
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// This will happen if the index is a known constant. This should ordinarily
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// be legalized out, but handle it as a register just in case.
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assert(Offset == 0);
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IdxBaseReg = IdxReg;
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}
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ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize);
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -784,3 +784,58 @@ body: |
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%4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: extract_vector_elt_s_s32_v4s32_const_idx
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; MOVREL-LABEL: name: extract_vector_elt_s_s32_v4s32_const_idx
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; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; MOVREL: $m0 = COPY [[S_MOV_B32_]]
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; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
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; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
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; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v4s32_const_idx
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; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GPRIDX: $m0 = COPY [[S_MOV_B32_]]
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; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
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; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
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%0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sgpr(s32) = G_CONSTANT i32 0
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%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: extract_vector_elt_v_s32_v4s32_const_idx
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; MOVREL-LABEL: name: extract_vector_elt_v_s32_v4s32_const_idx
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; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; MOVREL: $m0 = COPY [[S_MOV_B32_]]
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; MOVREL: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
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; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
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; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v4s32_const_idx
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; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GPRIDX: S_SET_GPR_IDX_ON [[S_MOV_B32_]], 1, implicit-def $m0, implicit $m0
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; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
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; GPRIDX: S_SET_GPR_IDX_OFF
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; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
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%0:vgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sgpr(s32) = G_CONSTANT i32 0
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%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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S_ENDPGM 0, implicit %2
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -624,3 +624,66 @@ body: |
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%5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
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S_ENDPGM 0, implicit %5
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...
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# This should have been folded out in the legalizer, but make sure it
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# doesn't crash.
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---
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name: insert_vector_elt_s_s32_v4s32_const_idx
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
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; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
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; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
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; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; MOVREL: $m0 = COPY [[S_MOV_B32_]]
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; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0
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; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V4_]]
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; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
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; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
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; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GPRIDX: $m0 = COPY [[S_MOV_B32_]]
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; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0
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; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V4_]]
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%0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sgpr(s32) = COPY $sgpr4
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%2:sgpr(s32) = G_CONSTANT i32 0
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%3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: insert_vector_elt_v_s32_v4s32_const_idx
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
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; MOVREL-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
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; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
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; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; MOVREL: $m0 = COPY [[S_MOV_B32_]]
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; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
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; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V4_]]
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; GPRIDX-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
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; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
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; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GPRIDX: S_SET_GPR_IDX_ON [[S_MOV_B32_]], 8, implicit-def $m0, implicit $m0
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; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
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; GPRIDX: S_SET_GPR_IDX_OFF
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; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V4_]]
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%0:vgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sgpr(s32) = COPY $sgpr4
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%2:sgpr(s32) = G_CONSTANT i32 0
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%3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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S_ENDPGM 0, implicit %3
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...

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