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[MLIR][Affine] Fix getAccessRelation for 0-d memrefs (#132347)
Fix getAccessRelation for 0-d memref accesses in certain cases. Fixes corner case crashes when using scalrep, affine dep analysis, etc. Fixes: #132163
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mlir/lib/Dialect/Affine/Analysis/AffineAnalysis.cpp

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -489,8 +489,11 @@ LogicalResult MemRefAccess::getAccessRelation(IntegerRelation &rel) const {
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// Append domain constraints to `rel`.
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IntegerRelation domainRel = domain;
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if (rel.getSpace().isUsingIds() && !domainRel.getSpace().isUsingIds())
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// For 0-d spaces, there will be no IDs. Enable if that's the case.
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if (!domainRel.getSpace().isUsingIds())
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domainRel.resetIds();
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if (!rel.getSpace().isUsingIds())
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rel.resetIds();
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domainRel.appendVar(VarKind::Range, accessValueMap.getNumResults());
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domainRel.mergeAndAlignSymbols(rel);
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domainRel.mergeLocalVars(rel);
@@ -660,6 +663,11 @@ DependenceResult mlir::affine::checkMemrefAccessDependence(
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// `srcAccess` to the iteration domain of `dstAccess` which access the same
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// memory locations.
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dstRel.inverse();
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// For 0-d spaces, there will be no IDs. Enable if that's the case.
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if (!dstRel.getSpace().isUsingIds())
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dstRel.resetIds();
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if (!srcRel.getSpace().isUsingIds())
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srcRel.resetIds();
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dstRel.mergeAndCompose(srcRel);
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dstRel.convertVarKind(VarKind::Domain, 0, dstRel.getNumDomainVars(),
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VarKind::Range, 0);

mlir/test/Dialect/Affine/scalrep.mlir

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -983,3 +983,17 @@ func.func @scf_for_if(%arg0: memref<?xi32>, %arg1: i32) -> i32 attributes {llvm.
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%3 = affine.load %0[0] : memref<1xi32>
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return %3 : i32
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}
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// CHECK-LABEL: func @zero_d_memrefs
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func.func @zero_d_memrefs() {
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// CHECK: %[[C0:.*]] = arith.constant 0
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%c0_i32 = arith.constant 0 : i32
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%alloc_0 = memref.alloc() {alignment = 64 : i64} : memref<i32>
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affine.store %c0_i32, %alloc_0[] : memref<i32>
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affine.for %arg0 = 0 to 9 {
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%2 = affine.load %alloc_0[] : memref<i32>
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arith.addi %2, %2 : i32
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// CHECK: arith.addi %[[C0]], %[[C0]]
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}
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return
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}

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