[FIXES]

Author: michaelmaitland

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -139,20 +139,25 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
       .clampScalar(0, s32, sXLen)
       .minScalarSameAs(1, 0);
 
-  auto &ExtActions =
-      getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
-          .customIf(typeIsLegalBoolVec(1, BoolVecTys, ST))
-          .legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
-                       typeIsLegalIntOrFPVec(1, IntOrFPVecTys, ST)))
-          .maxScalar(0, sXLen);
   if (ST.is64Bit()) {
-    ExtActions.legalFor({{sXLen, s32}});
+    getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
+        .customIf(typeIsLegalBoolVec(1, BoolVecTys, ST))
+        .legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
+                     typeIsLegalIntOrFPVec(1, IntOrFPVecTys, ST)))
+        .legalFor({{sXLen, s32}})
+        .maxScalar(0, sXLen);
 
     getActionDefinitionsBuilder(G_SEXT_INREG)
         .customFor({sXLen})
         .maxScalar(0, sXLen)
         .lower();
   } else {
+    getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
+        .customIf(typeIsLegalBoolVec(1, BoolVecTys, ST))
+        .legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
+                     typeIsLegalIntOrFPVec(1, IntOrFPVecTys, ST)))
+        .maxScalar(0, sXLen);
+
     getActionDefinitionsBuilder(G_SEXT_INREG).maxScalar(0, sXLen).lower();
   }
 

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

@@ -290,7 +290,16 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
   switch (Opc) {
   case TargetOpcode::G_ADD:
-  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_SUB: {
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {
+      LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+      return getInstructionMapping(
+          DefaultMappingID, /*Cost=*/1,
+          getVRBValueMapping(Ty.getSizeInBits().getKnownMinValue()),
+          NumOperands);
+    }
+  }
+    LLVM_FALLTHROUGH;
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT: {
@@ -496,9 +505,10 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
           getVRBValueMapping(DstTy.getSizeInBits().getKnownMinValue());
       OpdsMapping[2] = OpdsMapping[3] =
           getVRBValueMapping(SrcTy.getSizeInBits().getKnownMinValue());
+      break;
     }
-    break;
   }
+    LLVM_FALLTHROUGH;
   case TargetOpcode::G_FCMP: {
     LLT Ty = MRI.getType(MI.getOperand(2).getReg());
 

llvm/test/MachineVerifier/test_g_fcmp.mir

@@ -32,14 +32,14 @@ body:             |
 
     ; mismatched scalable element count
     ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of
-    %6:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
-    %7:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
-    %8:_(<vscale x 4 x s1>) = G_FCMP floatpred(oeq), %6, %7
+    %9:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+    %10:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+    %11:_(<vscale x 4 x s1>) = G_FCMP floatpred(oeq), %9, %10
 
     ; mismatched scalar element type
     ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
-    %9:_(s32) = G_FCONSTANT float 0.0
-    %10:_(s64) = G_FCONSTANT float 1.0
-    %11:_(s1) = G_FCMP floatpred(oeq), %9, %10
+    %12:_(s32) = G_FCONSTANT float 0.0
+    %13:_(s64) = G_FCONSTANT float 1.0
+    %14:_(s1) = G_FCMP floatpred(oeq), %12, %13
 
 ...

llvm/test/MachineVerifier/test_g_icmp.mir

@@ -32,14 +32,14 @@ body:             |
 
     ; mismatched scalable element count
     ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of
-    %6:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
-    %7:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
-    %8:_(<vscale x 4 x s1>) = G_ICMP intpred(eq), %6, %7
+    %9:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+    %10:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+    %11:_(<vscale x 4 x s1>) = G_ICMP intpred(eq), %9, %10
 
     ; mismatched scalar element type
     ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
-    %9:_(s32) = G_CONSTANT i32 0
-    %10:_(s64) = G_CONSTANT i32 1
-    %11:_(s1) = G_ICMP intpred(eq), %9, %10
+    %12:_(s32) = G_CONSTANT i32 0
+    %13:_(s64) = G_CONSTANT i32 1
+    %14:_(s1) = G_ICMP intpred(eq), %12, %13
 
 ...