address test comments

Author: epilk

llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir

@@ -1,17 +1,14 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s
 
 # Verify we maintain live-ins even if the first instruction in sched region is
 # DBG_.
 
 ---
 name:            sched
 tracksRegLiveness: true
-registers:
-- { id: 1, class: sgpr_32, preferred-register: '', flags: [  ] }
-- { id: 2, class: sgpr_32, preferred-register: '', flags: [  ] }
 body:             |
-  bb.0.entry:
+  bb.0:
     ; CHECK-LABEL: name: sched
     ; CHECK: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
     ; CHECK-NEXT: S_NOP 0
@@ -20,11 +17,11 @@ body:             |
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:sgpr_32 = COPY [[DEF]]
     ; CHECK-NEXT: S_NOP 0
     ; CHECK-NEXT: S_ENDPGM 0
-    %1:sgpr_32 = IMPLICIT_DEF
+    %0:sgpr_32 = IMPLICIT_DEF
     S_NOP 0
     SCHED_BARRIER 0
     DBG_VALUE
-    dead %2:sgpr_32 = COPY %1
+    dead %1:sgpr_32 = COPY %0
     S_NOP 0
     S_ENDPGM 0
 ...