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[AArch64][SVE][NFC] Add streaming mode SVE tests
Add sve-fixed-length testing files and enable streaming mode flag for: and-combine.ll bitcast.ll reshuffle.ll rev.ll sdiv-pow2.ll splat-vector.ll int-extends.ll Differential Revision: https://reviews.llvm.org/D137093
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll

Lines changed: 191 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; i8
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define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_4xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%c = and <4 x i8> %b, <i8 0, i8 255, i8 0, i8 255>
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ret <4 x i8> %c
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}
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define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_8xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%c = and <8 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
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ret <8 x i8> %c
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}
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define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI2_0
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%c = and <16 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
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ret <16 x i8> %c
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}
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define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_32xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z2.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: ret
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%b = and <32 x i8> %ap, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
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i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
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ret <32 x i8> %b
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}
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; i16
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define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_2xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z0.s, z0.s[1]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: stp wzr, w8, [sp, #8]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%c = and <2 x i16> %b, <i16 0, i16 65535>
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ret <2 x i16> %c
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}
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define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_4xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI5_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI5_0]
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%c = and <4 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535>
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ret <4 x i16> %c
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}
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define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_8xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI6_0
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%c = and <8 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535>
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ret <8 x i16> %c
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}
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define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_16xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI7_0
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z2.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: ret
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%c = and <16 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535>
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ret <16 x i16> %c
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}
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; i32
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define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_2xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: index z1.s, #0, #-1
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%c = and <2 x i32> %b, <i32 0, i32 4294967295>
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ret <2 x i32> %c
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}
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define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_4xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI9_0
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%c = and <4 x i32> %b, <i32 0, i32 4294967295, i32 0, i32 4294967295>
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ret <4 x i32> %c
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}
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define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_8xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI10_0
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_0]
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z2.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: ret
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%c = and <8 x i32> %b, <i32 0, i32 4294967295, i32 0, i32 4294967295, i32 0, i32 4294967295, i32 0, i32 4294967295>
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ret <8 x i32> %c
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}
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; i64
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define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_2xi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: index z1.d, #0, #-1
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%c = and <2 x i64> %b, <i64 0, i64 18446744073709551615>
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ret <2 x i64> %c
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}
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define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind #0 {
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; CHECK-LABEL: vls_sve_and_4xi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: index z2.d, #0, #-1
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z2.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: ret
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%c = and <4 x i64> %b, <i64 0, i64 18446744073709551615, i64 0, i64 18446744073709551615>
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ret <4 x i64> %c
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}
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attributes #0 = { "target-features"="+sve" }

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll

Lines changed: 198 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define void @bitcast_v4i8(<4 x i8> *%a, <4 x i8>* %b) #0 {
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; CHECK-LABEL: bitcast_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: uunpklo z0.h, z0.b
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; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <4 x i8>, <4 x i8>* %a
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%cast = bitcast <4 x i8> %load to <4 x i8>
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store volatile <4 x i8> %cast, <4 x i8>* %b
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ret void
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}
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define void @bitcast_v8i8(<8 x i8> *%a, <8 x i8>* %b) #0 {
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; CHECK-LABEL: bitcast_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <8 x i8>, <8 x i8>* %a
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%cast = bitcast <8 x i8> %load to <8 x i8>
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store volatile <8 x i8> %cast, <8 x i8>* %b
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ret void
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}
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define void @bitcast_v16i8(<16 x i8> *%a, <16 x i8>* %b) #0 {
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; CHECK-LABEL: bitcast_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <16 x i8>, <16 x i8>* %a
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%cast = bitcast <16 x i8> %load to <16 x i8>
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store volatile <16 x i8> %cast, <16 x i8>* %b
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ret void
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}
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define void @bitcast_v32i8(<32 x i8> *%a, <32 x i8>* %b) #0 {
45+
; CHECK-LABEL: bitcast_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: str q1, [x1, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <32 x i8>, <32 x i8>* %a
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%cast = bitcast <32 x i8> %load to <32 x i8>
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store volatile <32 x i8> %cast, <32 x i8>* %b
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ret void
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}
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define void @bitcast_v2i16(<2 x i16> *%a, <2 x half>* %b) #0 {
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; CHECK-LABEL: bitcast_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldrh w8, [x0, #2]
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; CHECK-NEXT: str w8, [sp, #4]
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: str w8, [sp]
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; CHECK-NEXT: ldr d0, [sp]
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; CHECK-NEXT: mov z1.s, z0.s[1]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: strh w9, [sp, #10]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%load = load volatile <2 x i16>, <2 x i16>* %a
79+
%cast = bitcast <2 x i16> %load to <2 x half>
80+
store volatile <2 x half> %cast, <2 x half>* %b
81+
ret void
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}
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define void @bitcast_v4i16(<4 x i16> *%a, <4 x half>* %b) #0 {
85+
; CHECK-LABEL: bitcast_v4i16:
86+
; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <4 x i16>, <4 x i16>* %a
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%cast = bitcast <4 x i16> %load to <4 x half>
92+
store volatile <4 x half> %cast, <4 x half>* %b
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ret void
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}
95+
96+
define void @bitcast_v8i16(<8 x i16> *%a, <8 x half>* %b) #0 {
97+
; CHECK-LABEL: bitcast_v8i16:
98+
; CHECK: // %bb.0:
99+
; CHECK-NEXT: ldr q0, [x0]
100+
; CHECK-NEXT: str q0, [x1]
101+
; CHECK-NEXT: ret
102+
%load = load volatile <8 x i16>, <8 x i16>* %a
103+
%cast = bitcast <8 x i16> %load to <8 x half>
104+
store volatile <8 x half> %cast, <8 x half>* %b
105+
ret void
106+
}
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108+
define void @bitcast_v16i16(<16 x i16> *%a, <16 x half>* %b) #0 {
109+
; CHECK-LABEL: bitcast_v16i16:
110+
; CHECK: // %bb.0:
111+
; CHECK-NEXT: ldr q0, [x0]
112+
; CHECK-NEXT: ldr q1, [x0, #16]
113+
; CHECK-NEXT: str q1, [x1, #16]
114+
; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
116+
%load = load volatile <16 x i16>, <16 x i16>* %a
117+
%cast = bitcast <16 x i16> %load to <16 x half>
118+
store volatile <16 x half> %cast, <16 x half>* %b
119+
ret void
120+
}
121+
122+
define void @bitcast_v2i32(<2 x i32> *%a, <2 x float>* %b) #0 {
123+
; CHECK-LABEL: bitcast_v2i32:
124+
; CHECK: // %bb.0:
125+
; CHECK-NEXT: ldr d0, [x0]
126+
; CHECK-NEXT: str d0, [x1]
127+
; CHECK-NEXT: ret
128+
%load = load volatile <2 x i32>, <2 x i32>* %a
129+
%cast = bitcast <2 x i32> %load to <2 x float>
130+
store volatile <2 x float> %cast, <2 x float>* %b
131+
ret void
132+
}
133+
134+
define void @bitcast_v4i32(<4 x i32> *%a, <4 x float>* %b) #0 {
135+
; CHECK-LABEL: bitcast_v4i32:
136+
; CHECK: // %bb.0:
137+
; CHECK-NEXT: ldr q0, [x0]
138+
; CHECK-NEXT: str q0, [x1]
139+
; CHECK-NEXT: ret
140+
%load = load volatile <4 x i32>, <4 x i32>* %a
141+
%cast = bitcast <4 x i32> %load to <4 x float>
142+
store volatile <4 x float> %cast, <4 x float>* %b
143+
ret void
144+
}
145+
146+
define void @bitcast_v8i32(<8 x i32> *%a, <8 x float>* %b) #0 {
147+
; CHECK-LABEL: bitcast_v8i32:
148+
; CHECK: // %bb.0:
149+
; CHECK-NEXT: ldr q0, [x0]
150+
; CHECK-NEXT: ldr q1, [x0, #16]
151+
; CHECK-NEXT: str q1, [x1, #16]
152+
; CHECK-NEXT: str q0, [x1]
153+
; CHECK-NEXT: ret
154+
%load = load volatile <8 x i32>, <8 x i32>* %a
155+
%cast = bitcast <8 x i32> %load to <8 x float>
156+
store volatile <8 x float> %cast, <8 x float>* %b
157+
ret void
158+
}
159+
160+
define void @bitcast_v1i64(<1 x i64> *%a, <1 x double>* %b) #0 {
161+
; CHECK-LABEL: bitcast_v1i64:
162+
; CHECK: // %bb.0:
163+
; CHECK-NEXT: ldr d0, [x0]
164+
; CHECK-NEXT: str d0, [x1]
165+
; CHECK-NEXT: ret
166+
%load = load volatile <1 x i64>, <1 x i64>* %a
167+
%cast = bitcast <1 x i64> %load to <1 x double>
168+
store volatile <1 x double> %cast, <1 x double>* %b
169+
ret void
170+
}
171+
172+
define void @bitcast_v2i64(<2 x i64> *%a, <2 x double>* %b) #0 {
173+
; CHECK-LABEL: bitcast_v2i64:
174+
; CHECK: // %bb.0:
175+
; CHECK-NEXT: ldr q0, [x0]
176+
; CHECK-NEXT: str q0, [x1]
177+
; CHECK-NEXT: ret
178+
%load = load volatile <2 x i64>, <2 x i64>* %a
179+
%cast = bitcast <2 x i64> %load to <2 x double>
180+
store volatile <2 x double> %cast, <2 x double>* %b
181+
ret void
182+
}
183+
184+
define void @bitcast_v4i64(<4 x i64> *%a, <4 x double>* %b) #0 {
185+
; CHECK-LABEL: bitcast_v4i64:
186+
; CHECK: // %bb.0:
187+
; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: str q1, [x1, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <4 x i64>, <4 x i64>* %a
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%cast = bitcast <4 x i64> %load to <4 x double>
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store volatile <4 x double> %cast, <4 x double>* %b
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ret void
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}
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attributes #0 = { "target-features"="+sve" }

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