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AMDGPU: Replace ptr addrspace(3) undef in tests with poison
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lines changed

‎llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ define amdgpu_kernel void @infer_ptr_alignment_global_offset(ptr addrspace(1) %o
9292
}
9393

9494

95-
@ptr = addrspace(3) global ptr addrspace(3) undef
95+
@ptr = addrspace(3) global ptr addrspace(3) poison
9696
@dst = addrspace(3) global [16383 x i32] undef
9797

9898
; FUNC-LABEL: {{^}}global_ptr:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1619,7 +1619,7 @@ define amdgpu_ps void @dyn_extract_v8p3_s_s(<8 x ptr addrspace(3)> inreg %vec, i
16191619
; GFX11-NEXT: s_endpgm
16201620
entry:
16211621
%ext = extractelement <8 x ptr addrspace(3)> %vec, i32 %idx
1622-
store ptr addrspace(3) %ext, ptr addrspace(3) undef
1622+
store ptr addrspace(3) %ext, ptr addrspace(3) poison
16231623
ret void
16241624
}
16251625

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ define float @v_test_fmax_legacy_ule_f32_multi_use(float %a, float %b) {
229229
%cmp = fcmp ogt float %a, %b
230230
%val0 = select i1 %cmp, float %a, float %b
231231
%val1 = zext i1 %cmp to i32
232-
store i32 %val1, ptr addrspace(3) undef
232+
store i32 %val1, ptr addrspace(3) poison
233233
ret float %val0
234234
}
235235

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,7 @@ define float @v_test_fmin_legacy_ule_f32_multi_use(float %a, float %b) {
212212
%cmp = fcmp ule float %a, %b
213213
%val0 = select i1 %cmp, float %a, float %b
214214
%val1 = zext i1 %cmp to i32
215-
store i32 %val1, ptr addrspace(3) undef
215+
store i32 %val1, ptr addrspace(3) poison
216216
ret float %val0
217217
}
218218

‎llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,10 +1062,10 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
10621062
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
10631063
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
10641064
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
1065-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1066-
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1067-
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1068-
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1065+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
1066+
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
1067+
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
1068+
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
10691069
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], [[LOAD]](s32), [[C]](s32)
10701070
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[LOAD1]](s32), [[C1]](s32)
10711071
; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[LOAD2]](s32), [[C2]](s32)
@@ -1075,10 +1075,10 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
10751075
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
10761076
; CHECK-NEXT: $vgpr3 = COPY [[LOAD3]](s32)
10771077
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
1078-
%load0 = load volatile i32, ptr addrspace(3) undef
1079-
%load1 = load volatile i32, ptr addrspace(3) undef
1080-
%load2 = load volatile i32, ptr addrspace(3) undef
1081-
%load3 = load volatile i32, ptr addrspace(3) undef
1078+
%load0 = load volatile i32, ptr addrspace(3) poison
1079+
%load1 = load volatile i32, ptr addrspace(3) poison
1080+
%load2 = load volatile i32, ptr addrspace(3) poison
1081+
%load3 = load volatile i32, ptr addrspace(3) poison
10821082

10831083
%insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0
10841084
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
@@ -1097,10 +1097,10 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
10971097
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
10981098
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
10991099
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
1100-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1101-
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1102-
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1103-
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
1100+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
1101+
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
1102+
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
1103+
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
11041104
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], [[LOAD]](s32), [[C]](s32)
11051105
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[LOAD1]](s32), [[C1]](s32)
11061106
; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[LOAD2]](s32), [[C2]](s32)
@@ -1110,10 +1110,10 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
11101110
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
11111111
; CHECK-NEXT: $vgpr3 = COPY [[LOAD3]](s32)
11121112
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
1113-
%load0 = load volatile float, ptr addrspace(3) undef
1114-
%load1 = load volatile float, ptr addrspace(3) undef
1115-
%load2 = load volatile float, ptr addrspace(3) undef
1116-
%load3 = load volatile i32, ptr addrspace(3) undef
1113+
%load0 = load volatile float, ptr addrspace(3) poison
1114+
%load1 = load volatile float, ptr addrspace(3) poison
1115+
%load2 = load volatile float, ptr addrspace(3) poison
1116+
%load3 = load volatile i32, ptr addrspace(3) poison
11171117

11181118
%insert.0 = insertelement <3 x float> poison, float %load0, i32 0
11191119
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
@@ -1137,19 +1137,19 @@ define void @void_func_sret_max_known_zero_bits(ptr addrspace(5) sret(i8) %arg0)
11371137
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
11381138
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
11391139
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
1140-
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
1141-
; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
1142-
; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
1140+
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
1141+
; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
1142+
; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
11431143
; CHECK-NEXT: SI_RETURN
11441144
%arg0.int = ptrtoint ptr addrspace(5) %arg0 to i32
11451145

11461146
%lshr0 = lshr i32 %arg0.int, 16
11471147
%lshr1 = lshr i32 %arg0.int, 17
11481148
%lshr2 = lshr i32 %arg0.int, 18
11491149

1150-
store volatile i32 %lshr0, ptr addrspace(3) undef
1151-
store volatile i32 %lshr1, ptr addrspace(3) undef
1152-
store volatile i32 %lshr2, ptr addrspace(3) undef
1150+
store volatile i32 %lshr0, ptr addrspace(3) poison
1151+
store volatile i32 %lshr1, ptr addrspace(3) poison
1152+
store volatile i32 %lshr2, ptr addrspace(3) poison
11531153
ret void
11541154
}
11551155

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1239,10 +1239,10 @@ define amdgpu_kernel void @test_call_external_p3_func_void() #0 {
12391239
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_p3_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
12401240
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0
12411241
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
1242-
; GCN-NEXT: G_STORE [[COPY21]](p3), [[DEF]](p3) :: (volatile store (p3) into `ptr addrspace(3) undef`, addrspace 3)
1242+
; GCN-NEXT: G_STORE [[COPY21]](p3), [[DEF]](p3) :: (volatile store (p3) into `ptr addrspace(3) poison`, addrspace 3)
12431243
; GCN-NEXT: S_ENDPGM 0
12441244
%val = call ptr addrspace(3) @external_p3_func_void()
1245-
store volatile ptr addrspace(3) %val, ptr addrspace(3) undef
1245+
store volatile ptr addrspace(3) %val, ptr addrspace(3) poison
12461246
ret void
12471247
}
12481248

@@ -1299,10 +1299,10 @@ define amdgpu_kernel void @test_call_external_v2p3_func_void() #0 {
12991299
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(p3) = COPY $vgpr1
13001300
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY21]](p3), [[COPY22]](p3)
13011301
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
1302-
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `ptr addrspace(3) undef`, addrspace 3)
1302+
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `ptr addrspace(3) poison`, addrspace 3)
13031303
; GCN-NEXT: S_ENDPGM 0
13041304
%val = call <2 x ptr addrspace(3)> @external_v2p3_func_void()
1305-
store volatile <2 x ptr addrspace(3)> %val, ptr addrspace(3) undef
1305+
store volatile <2 x ptr addrspace(3)> %val, ptr addrspace(3) poison
13061306
ret void
13071307
}
13081308

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1699,13 +1699,13 @@ define void @void_func_byval_struct_i8_i32_x2(ptr addrspace(5) byval({ i8, i32 }
16991699
; CHECK-NEXT: G_STORE [[LOAD2]](s8), [[DEF]](p1) :: (volatile store (s8) into `ptr addrspace(1) poison`, align 4, addrspace 1)
17001700
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[DEF]], [[C1]](s64)
17011701
; CHECK-NEXT: G_STORE [[LOAD3]](s32), [[PTR_ADD3]](p1) :: (volatile store (s32) into `ptr addrspace(1) poison` + 4, addrspace 1)
1702-
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[DEF1]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
1702+
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[DEF1]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
17031703
; CHECK-NEXT: SI_RETURN
17041704
%arg0.load = load volatile { i8, i32 }, ptr addrspace(5) %arg0
17051705
%arg1.load = load volatile { i8, i32 }, ptr addrspace(5) %arg1
17061706
store volatile { i8, i32 } %arg0.load, ptr addrspace(1) poison
17071707
store volatile { i8, i32 } %arg1.load, ptr addrspace(1) poison
1708-
store volatile i32 %arg2, ptr addrspace(3) undef
1708+
store volatile i32 %arg2, ptr addrspace(3) poison
17091709
ret void
17101710
}
17111711

@@ -2540,18 +2540,18 @@ define void @void_func_v3f32_wasted_reg(<3 x float> %arg0, i32 %arg1) #0 {
25402540
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)
25412541
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)
25422542
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)
2543-
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2544-
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2545-
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2546-
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2543+
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
2544+
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
2545+
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
2546+
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
25472547
; CHECK-NEXT: SI_RETURN
25482548
%arg0.0 = extractelement <3 x float> %arg0, i32 0
25492549
%arg0.1 = extractelement <3 x float> %arg0, i32 1
25502550
%arg0.2 = extractelement <3 x float> %arg0, i32 2
2551-
store volatile float %arg0.0, ptr addrspace(3) undef
2552-
store volatile float %arg0.1, ptr addrspace(3) undef
2553-
store volatile float %arg0.2, ptr addrspace(3) undef
2554-
store volatile i32 %arg1, ptr addrspace(3) undef
2551+
store volatile float %arg0.0, ptr addrspace(3) poison
2552+
store volatile float %arg0.1, ptr addrspace(3) poison
2553+
store volatile float %arg0.2, ptr addrspace(3) poison
2554+
store volatile i32 %arg1, ptr addrspace(3) poison
25552555
ret void
25562556
}
25572557

@@ -2572,18 +2572,18 @@ define void @void_func_v3i32_wasted_reg(<3 x i32> %arg0, i32 %arg1) #0 {
25722572
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)
25732573
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)
25742574
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)
2575-
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2576-
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2577-
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2578-
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
2575+
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
2576+
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
2577+
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
2578+
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
25792579
; CHECK-NEXT: SI_RETURN
25802580
%arg0.0 = extractelement <3 x i32> %arg0, i32 0
25812581
%arg0.1 = extractelement <3 x i32> %arg0, i32 1
25822582
%arg0.2 = extractelement <3 x i32> %arg0, i32 2
2583-
store volatile i32 %arg0.0, ptr addrspace(3) undef
2584-
store volatile i32 %arg0.1, ptr addrspace(3) undef
2585-
store volatile i32 %arg0.2, ptr addrspace(3) undef
2586-
store volatile i32 %arg1, ptr addrspace(3) undef
2583+
store volatile i32 %arg0.0, ptr addrspace(3) poison
2584+
store volatile i32 %arg0.1, ptr addrspace(3) poison
2585+
store volatile i32 %arg0.2, ptr addrspace(3) poison
2586+
store volatile i32 %arg1, ptr addrspace(3) poison
25872587
ret void
25882588
}
25892589

‎llvm/test/CodeGen/AMDGPU/add.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1389,7 +1389,7 @@ define amdgpu_ps void @add_select_vop3(i32 inreg %s, i32 %v) {
13891389
; GFX12-NEXT: s_endpgm
13901390
%vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
13911391
%sub = add i32 %v, %s
1392-
store i32 %sub, ptr addrspace(3) undef
1392+
store i32 %sub, ptr addrspace(3) poison
13931393
call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc)
13941394
ret void
13951395
}

‎llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -863,7 +863,7 @@ bb16: ; preds = %bb58, %bb14
863863
%i34 = getelementptr inbounds [16 x half], ptr addrspace(1) null, i64 %i24, i64 14
864864
%i36 = load volatile <2 x half>, ptr addrspace(1) %i34, align 4
865865
%i43 = load volatile <2 x float>, ptr addrspace(3) null, align 8
866-
%i46 = load volatile <2 x float>, ptr addrspace(3) undef, align 32
866+
%i46 = load volatile <2 x float>, ptr addrspace(3) poison, align 32
867867
fence syncscope("workgroup") acquire
868868
br i1 %i11, label %bb58, label %bb51
869869

‎llvm/test/CodeGen/AMDGPU/branch-condition-and.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ bb:
3131
br i1 %tmp3, label %bb4, label %bb5
3232

3333
bb4: ; preds = %bb
34-
store volatile i32 4, ptr addrspace(3) undef
34+
store volatile i32 4, ptr addrspace(3) poison
3535
unreachable
3636

3737
bb5: ; preds = %bb

‎llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -607,7 +607,7 @@ done:
607607
; OPT-LABEL: @test_wrong_operand_local_small_offset_cmpxchg_i32(
608608
; OPT: %in.gep = getelementptr i32, ptr addrspace(3) %in, i32 7
609609
; OPT: br i1
610-
; OPT: cmpxchg ptr addrspace(3) undef, ptr addrspace(3) %in.gep, ptr addrspace(3) undef seq_cst monotonic
610+
; OPT: cmpxchg ptr addrspace(3) poison, ptr addrspace(3) %in.gep, ptr addrspace(3) poison seq_cst monotonic
611611
define amdgpu_kernel void @test_wrong_operand_local_small_offset_cmpxchg_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) {
612612
entry:
613613
%out.gep = getelementptr ptr addrspace(3), ptr addrspace(3) %out, i32 999999
@@ -617,7 +617,7 @@ entry:
617617
br i1 %tmp0, label %endif, label %if
618618

619619
if:
620-
%tmp1.struct = cmpxchg ptr addrspace(3) undef, ptr addrspace(3) %in.gep, ptr addrspace(3) undef seq_cst monotonic
620+
%tmp1.struct = cmpxchg ptr addrspace(3) poison, ptr addrspace(3) %in.gep, ptr addrspace(3) poison seq_cst monotonic
621621
%tmp1 = extractvalue { ptr addrspace(3), i1 } %tmp1.struct, 0
622622
br label %endif
623623

‎llvm/test/CodeGen/AMDGPU/concat_vectors.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -313,7 +313,7 @@ define amdgpu_kernel void @concat_vector_crash2(ptr addrspace(1) %out, ptr addrs
313313
; VI: ds_write_b128
314314
define amdgpu_kernel void @build_vector_splat_concat_v8i16() {
315315
entry:
316-
store <8 x i16> zeroinitializer, ptr addrspace(3) undef, align 16
316+
store <8 x i16> zeroinitializer, ptr addrspace(3) poison, align 16
317317
store <8 x i16> zeroinitializer, ptr addrspace(3) null, align 16
318318
ret void
319319
}

‎llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -66,12 +66,12 @@
6666
define amdgpu_kernel void @divergent_if_endif(ptr addrspace(1) %out) #0 {
6767
entry:
6868
%tid = call i32 @llvm.amdgcn.workitem.id.x()
69-
%load0 = load volatile i32, ptr addrspace(3) undef
69+
%load0 = load volatile i32, ptr addrspace(3) poison
7070
%cmp0 = icmp eq i32 %tid, 0
7171
br i1 %cmp0, label %if, label %endif
7272

7373
if:
74-
%load1 = load volatile i32, ptr addrspace(3) undef
74+
%load1 = load volatile i32, ptr addrspace(3) poison
7575
%val = add i32 %load0, %load1
7676
br label %endif
7777

@@ -145,7 +145,7 @@ entry:
145145
loop:
146146
%i = phi i32 [ %i.inc, %loop ], [ 0, %entry ]
147147
%val = phi i32 [ %val.sub, %loop ], [ %load0, %entry ]
148-
%load1 = load volatile i32, ptr addrspace(3) undef
148+
%load1 = load volatile i32, ptr addrspace(3) poison
149149
%i.inc = add i32 %i, 1
150150
%val.sub = sub i32 %val, %load1
151151
%cmp1 = icmp ne i32 %i, 256
@@ -257,12 +257,12 @@ entry:
257257
br i1 %cmp0, label %if, label %else
258258

259259
if:
260-
%load1 = load volatile i32, ptr addrspace(3) undef
260+
%load1 = load volatile i32, ptr addrspace(3) poison
261261
%val0 = add i32 %load0, %load1
262262
br label %endif
263263

264264
else:
265-
%load2 = load volatile i32, ptr addrspace(3) undef
265+
%load2 = load volatile i32, ptr addrspace(3) poison
266266
%val1 = sub i32 %load0, %load2
267267
br label %endif
268268

‎llvm/test/CodeGen/AMDGPU/fminnum.f64.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,10 +47,10 @@ define amdgpu_kernel void @test_fmin_f64_ieee_flush([8 x i32], double %a, [8 x i
4747
; GCN-NOT: [[RESULT]]
4848
; GCN: ds_write_b64 v{{[0-9]+}}, [[RESULT]]
4949
define amdgpu_ps void @test_fmin_f64_no_ieee() nounwind {
50-
%a = load volatile double, ptr addrspace(3) undef
51-
%b = load volatile double, ptr addrspace(3) undef
50+
%a = load volatile double, ptr addrspace(3) poison
51+
%b = load volatile double, ptr addrspace(3) poison
5252
%val = call double @llvm.minnum.f64(double %a, double %b) #0
53-
store volatile double %val, ptr addrspace(3) undef
53+
store volatile double %val, ptr addrspace(3) poison
5454
ret void
5555
}
5656

‎llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
180180
; G_GFX1030-NEXT: s_endpgm
181181
main_body:
182182
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
183-
store double %ret, ptr addrspace(3) undef
183+
store double %ret, ptr addrspace(3) poison
184184
ret void
185185
}
186186

@@ -417,7 +417,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
417417
; G_GFX1030-NEXT: s_endpgm
418418
main_body:
419419
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
420-
store double %ret, ptr addrspace(3) undef
420+
store double %ret, ptr addrspace(3) poison
421421
ret void
422422
}
423423

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