[MTE] Do not allow local aliases to MTE globals (#106280)

With this change and appropriate linker changes
(https://r.android.com/3236256)
AOSP boots with memtag-global throughout the platform.

Without this change, we would sometimes generate PC-relative references
to tagged globals, which then do not have the proper tag.

Author: fmayer

llvm/lib/IR/Globals.cpp

@@ -110,6 +110,12 @@ bool GlobalValue::isInterposable() const {
 }
 
 bool GlobalValue::canBenefitFromLocalAlias() const {
+  if (isTagged()) {
+    // Cannot create local aliases to MTE tagged globals. The address of a
+    // tagged global includes a tag that is assigned by the loader in the
+    // GOT.
+    return false;
+  }
   // See AsmPrinter::getSymbolPreferLocal(). For a deduplicate comdat kind,
   // references to a discarded local symbol from outside the group are not
   // allowed, so avoid the local alias.

llvm/test/CodeGen/AArch64/semantic-interposition-memtag.ll

@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -relocation-model=pic  < %s | FileCheck %s
+
+;; Test that we use do not the local alias for dso_local globals with MTE.
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "aarch64-unknown-linux-android10000"
+
+@x = dso_local global i32 1, sanitize_memtag, align 4
+@y = dso_local global i32 1, align 4
+
+; Function Attrs: noinline optnone
+define dso_local i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK:       .Lmain$local:
+; CHECK-NEXT:    .type .Lmain$local,@function
+; CHECK-NEXT:    .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:x
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:x]
+; CHECK-NEXT:    ldr w0, [x8]
+; CHECK-NEXT:    ret
+entry:
+  %0 = load i32, ptr @x, align 4
+  ret i32 %0
+}
+
+; Function Attrs: noinline optnone
+define dso_local i32 @main2() #0 {
+; CHECK-LABEL: main2:
+; CHECK:       .Lmain2$local:
+; CHECK-NEXT:    .type .Lmain2$local,@function
+; CHECK-NEXT:    .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, .Ly$local
+; CHECK-NEXT:    add x8, x8, :lo12:.Ly$local
+; CHECK-NEXT:    ldr w0, [x8]
+; CHECK-NEXT:    ret
+entry:
+  %0 = load i32, ptr @y, align 4
+  ret i32 %0
+}
+
+
+attributes #0 = { noinline optnone "target-cpu"="generic" "target-features"="+mte,+v8a" }
+
+!llvm.module.flags = !{!2, !3}
+
+!2 = !{i32 8, !"PIC Level", i32 2}
+!3 = !{i32 7, !"PIE Level", i32 0}