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davemgreendavemgreen
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[AArch64] Additional tests for negative SVE addressing modes. NFC
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‎llvm/test/CodeGen/AArch64/sve-reassocadd.ll

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@@ -181,4 +181,149 @@ entry:
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ret <vscale x 2 x i64> %2
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}
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define <vscale x 16 x i8> @i8_m2v_4s(ptr %b) {
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; CHECK-LABEL: i8_m2v_4s:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: mov w9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 %1
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 4
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%2 = load <vscale x 16 x i8>, ptr %add.ptr1, align 16
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ret <vscale x 16 x i8> %2
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}
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define <vscale x 16 x i8> @i8_4s_m2v(ptr %b) {
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; CHECK-LABEL: i8_4s_m2v:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: mov w9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9]
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; CHECK-NEXT: ret
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entry:
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 4
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 %1
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%2 = load <vscale x 16 x i8>, ptr %add.ptr1, align 16
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ret <vscale x 16 x i8> %2
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}
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define <vscale x 8 x i16> @i16_m2v_8s(ptr %b) {
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; CHECK-LABEL: i16_m2v_8s:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: mov x9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 %1
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 8
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%2 = load <vscale x 8 x i16>, ptr %add.ptr1, align 16
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ret <vscale x 8 x i16> %2
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}
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define <vscale x 8 x i16> @i16_8s_m2v(ptr %b) {
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; CHECK-LABEL: i16_8s_m2v:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: mov x9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
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; CHECK-NEXT: ret
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entry:
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 8
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 %1
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%2 = load <vscale x 8 x i16>, ptr %add.ptr1, align 16
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ret <vscale x 8 x i16> %2
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}
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define <vscale x 4 x i32> @i32_m2v_16s(ptr %b) {
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; CHECK-LABEL: i32_m2v_16s:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mov x9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 %1
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 16
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%2 = load <vscale x 4 x i32>, ptr %add.ptr1, align 16
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @i32_16s_m2v(ptr %b) {
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; CHECK-LABEL: i32_16s_m2v:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mov x9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
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; CHECK-NEXT: ret
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entry:
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 16
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 %1
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%2 = load <vscale x 4 x i32>, ptr %add.ptr1, align 16
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 2 x i64> @i64_m2v_32s(ptr %b) {
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; CHECK-LABEL: i64_m2v_32s:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov x9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 %1
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 32
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%2 = load <vscale x 2 x i64>, ptr %add.ptr1, align 16
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ret <vscale x 2 x i64> %2
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}
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define <vscale x 2 x i64> @i64_32s_m2v(ptr %b) {
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; CHECK-LABEL: i64_32s_m2v:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cnth x8, all, mul #4
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov x9, #4 // =0x4
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3]
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; CHECK-NEXT: ret
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entry:
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%add.ptr = getelementptr inbounds i8, ptr %b, i64 32
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = mul i64 %0, -32
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%add.ptr1 = getelementptr inbounds i8, ptr %add.ptr, i64 %1
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%2 = load <vscale x 2 x i64>, ptr %add.ptr1, align 16
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ret <vscale x 2 x i64> %2
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}
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declare i64 @llvm.vscale.i64()

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