[RISCV] Run mem2reg on more scalar C builtin tests to remove allocas and simplify checks. NFC

Author: topperc

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c

@@ -1,38 +1,30 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBB
 
 // RV32ZBB-LABEL: @orc_b_32(
 // RV32ZBB-NEXT:  entry:
-// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
-// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int orc_b_32(unsigned int a) {
   return __builtin_riscv_orc_b_32(a);
 }
 
 // RV32ZBB-LABEL: @clz_32(
 // RV32ZBB-NEXT:  entry:
-// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
-// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
 // RV32ZBB-LABEL: @ctz_32(
 // RV32ZBB-NEXT:  entry:
-// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
-// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

@@ -1,50 +1,39 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBB
 
 // RV64ZBB-LABEL: @orc_b_32(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
-// RV64ZBB-NEXT:    ret i32 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
+// RV64ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int orc_b_32(unsigned int a) {
   return __builtin_riscv_orc_b_32(a);
 }
 
 // RV64ZBB-LABEL: @orc_b_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]])
-// RV64ZBB-NEXT:    ret i64 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[A:%.*]])
+// RV64ZBB-NEXT:    ret i64 [[TMP0]]
 //
 unsigned long orc_b_64(unsigned long a) {
   return __builtin_riscv_orc_b_64(a);
 }
 
 // RV64ZBB-LABEL: @clz_32(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    ret i32 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
 // RV64ZBB-LABEL: @clz_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
 // RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
 unsigned int clz_64(unsigned long a) {
@@ -53,23 +42,17 @@ unsigned int clz_64(unsigned long a) {
 
 // RV64ZBB-LABEL: @ctz_32(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    ret i32 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
 // RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
 unsigned int ctz_64(unsigned long a) {