[MC] Do not copy MCInstrDescs. NFC.

Avoid copying MCInstrDesc instances because a future patch will change
them to find their implicit operands and operand info array based on
their own "this" pointer, so it will only work for MCInstrDescs in the
TargetInsts table, not for a copy of an MCInstrDesc at a different
address.

Differential Revision: https://reviews.llvm.org/D142214

Author: jayfoad

llvm/include/llvm/MC/MCInstrDesc.h

@@ -197,6 +197,14 @@ enum Flag {
 /// directly to describe itself.
 class MCInstrDesc {
 public:
+  // Do not allow MCInstrDescs to be copied or moved. They should only exist in
+  // the <Target>Insts table because they rely on knowing their own address to
+  // find other information elsewhere in the same table.
+  MCInstrDesc(const MCInstrDesc &) = delete;
+  MCInstrDesc(MCInstrDesc &&) = delete;
+  MCInstrDesc &operator=(const MCInstrDesc &) = delete;
+  MCInstrDesc &operator=(MCInstrDesc &&) = delete;
+
   unsigned short Opcode;         // The opcode number
   unsigned short NumOperands;    // Num of args (may be more if variable_ops)
   unsigned char NumDefs;         // Num of args that are definitions

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

@@ -340,7 +340,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
     }
 
     unsigned Idx = RegDefPos.GetIdx();
-    const MCInstrDesc Desc = TII->get(Opcode);
+    const MCInstrDesc &Desc = TII->get(Opcode);
     const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
     assert(RC && "Not a valid register class");
     RegClass = RC->getID();

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

@@ -2938,7 +2938,7 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
       SDNode * User = *U;
       if (User->isMachineOpcode()) {
         unsigned Opc = User->getMachineOpcode();
-        MCInstrDesc Desc = SII->get(Opc);
+        const MCInstrDesc &Desc = SII->get(Opc);
         if (Desc.isCommutable()) {
           unsigned OpIdx = Desc.getNumDefs() + U.getOperandNo();
           unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -2452,7 +2452,8 @@ bool SIInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
   return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
 }
 
-bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
+bool SIInstrInfo::findCommutedOpIndices(const MCInstrDesc &Desc,
+                                        unsigned &SrcOpIdx0,
                                         unsigned &SrcOpIdx1) const {
   if (!Desc.isCommutable())
     return false;

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -268,7 +268,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
                              unsigned &SrcOpIdx1) const override;
 
-  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
+  bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
                              unsigned &SrcOpIdx1) const;
 
   bool isBranchOffsetInRange(unsigned BranchOpc,

llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp

@@ -224,7 +224,7 @@ void Filler::insertDefsUses(MachineBasicBlock::instr_iterator MI,
                             SmallSet<unsigned, 32> &RegDefs,
                             SmallSet<unsigned, 32> &RegUses) {
   // If MI is a call or return, just examine the explicit non-variadic operands.
-  MCInstrDesc MCID = MI->getDesc();
+  const MCInstrDesc &MCID = MI->getDesc();
   unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands()
                                               : MI->getNumOperands();
   for (unsigned I = 0; I != E; ++I) {

llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp

@@ -80,7 +80,7 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
     printOpExtInst(MI, OS);
   } else {
     // Print any extra operands for variadic instructions.
-    MCInstrDesc MCDesc = MII.get(OpCode);
+    const MCInstrDesc &MCDesc = MII.get(OpCode);
     if (MCDesc.isVariadic()) {
       const unsigned NumFixedOps = MCDesc.getNumOperands();
       const unsigned LastFixedIndex = NumFixedOps - 1;
@@ -185,7 +185,7 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
 void SPIRVInstPrinter::printOpExtInst(const MCInst *MI, raw_ostream &O) {
   // The fixed operands have already been printed, so just need to decide what
   // type of ExtInst operands to print based on the instruction set and number.
-  MCInstrDesc MCDesc = MII.get(MI->getOpcode());
+  const MCInstrDesc &MCDesc = MII.get(MI->getOpcode());
   unsigned NumFixedOps = MCDesc.getNumOperands();
   const auto NumOps = MI->getNumOperands();
   if (NumOps == NumFixedOps)
@@ -200,7 +200,7 @@ void SPIRVInstPrinter::printOpExtInst(const MCInst *MI, raw_ostream &O) {
 void SPIRVInstPrinter::printOpDecorate(const MCInst *MI, raw_ostream &O) {
   // The fixed operands have already been printed, so just need to decide what
   // type of decoration operands to print based on the Decoration type.
-  MCInstrDesc MCDesc = MII.get(MI->getOpcode());
+  const MCInstrDesc &MCDesc = MII.get(MI->getOpcode());
   unsigned NumFixedOps = MCDesc.getNumOperands();
 
   if (NumFixedOps != MI->getNumOperands()) {

llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp

@@ -61,7 +61,7 @@ using EndianWriter = support::endian::Writer;
 // output register in operand 0. If so, we need to swap operands 0 and 1 so the
 // type comes first in the output, despide coming second in the MCInst.
 static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
-  MCInstrDesc MCDesc = MII.get(MI.getOpcode());
+  const MCInstrDesc &MCDesc = MII.get(MI.getOpcode());
   // If we define an output, and have at least one other argument.
   if (MCDesc.getNumDefs() == 1 && MCDesc.getNumOperands() >= 2) {
     // Check if we define an ID, and take a type as operand 1.

llvm/unittests/CodeGen/LexicalScopesTest.cpp

@@ -58,8 +58,8 @@ class LexicalScopesTest : public testing::Test {
   // Some meaningless instructions -- the first is fully meaningless,
   // while the second is supposed to impersonate DBG_VALUEs through its
   // opcode.
-  MCInstrDesc BeanInst;
-  MCInstrDesc DbgValueInst;
+  MCInstrDesc BeanInst{};
+  MCInstrDesc DbgValueInst{};
 
   LexicalScopesTest() : Ctx(), Mod("beehives", Ctx) {
     memset(&BeanInst, 0, sizeof(BeanInst));