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[SelectionDAGBuilder] Simplify visitShift. NFC
This code was detecting whether the value returned by getShiftAmountTy can represent all shift amounts. If not, it would use MVT::i32 as a placeholder. getShiftAmountTy was updated last year to return i32 if the type returned by the target couldn't represent all values. This means the MVT::i32 case here is dead and can the logic can be simplified. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D120164
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llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 5 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -3150,26 +3150,12 @@ void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
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EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
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Op1.getValueType(), DAG.getDataLayout());
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// Coerce the shift amount to the right type if we can.
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// Coerce the shift amount to the right type if we can. This exposes the
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// truncate or zext to optimization early.
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if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
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unsigned ShiftSize = ShiftTy.getSizeInBits();
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unsigned Op2Size = Op2.getValueSizeInBits();
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SDLoc DL = getCurSDLoc();
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// If the operand is smaller than the shift count type, promote it.
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if (ShiftSize > Op2Size)
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Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
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// If the operand is larger than the shift count type but the shift
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// count type has enough bits to represent any shift value, truncate
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// it now. This is a common case and it exposes the truncate to
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// optimization early.
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else if (ShiftSize >= Log2_32_Ceil(Op1.getValueSizeInBits()))
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Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
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// Otherwise we'll need to temporarily settle for some other convenient
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// type. Type legalization will make adjustments once the shiftee is split.
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else
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Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
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assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) &&
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"Unexpected shift type");
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Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy);
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}
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bool nuw = false;

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