Skip to content

Commit 24c8d90

Browse files
tclin914tclin914
authored
[RISCV] Remove B and Zbc extension from Andes series cpus. (#144022)
The Andes CPU is configurable with optional extensions. The minimal required extension set does not include `B` and `Zbc` extensions. So we decided to remove them.
1 parent 4ed10db commit 24c8d90

File tree

8 files changed

+7
-41
lines changed

8 files changed

+7
-41
lines changed

‎clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13-
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1413
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1514
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1615
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@@ -19,12 +18,8 @@
1918
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
2019
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
2120
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22-
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23-
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24-
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
25-
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2621
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2722
// CHECK-EMPTY:
2823
// CHECK-NEXT: Experimental extensions
2924
// CHECK-EMPTY:
30-
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
25+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13-
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1413
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1514
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1615
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@@ -19,11 +18,8 @@
1918
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
2019
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
2120
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22-
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23-
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24-
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2521
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2622
// CHECK-EMPTY:
2723
// CHECK-NEXT: Experimental extensions
2824
// CHECK-EMPTY:
29-
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
25+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,20 +10,15 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13-
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1413
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1514
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1615
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
1716
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
1817
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
1918
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
2019
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21-
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22-
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23-
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
24-
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2520
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2621
// CHECK-EMPTY:
2722
// CHECK-NEXT: Experimental extensions
2823
// CHECK-EMPTY:
29-
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
24+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,15 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13-
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1413
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1514
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1615
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
1716
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
1817
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
1918
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
2019
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21-
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22-
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23-
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2420
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2521
// CHECK-EMPTY:
2622
// CHECK-NEXT: Experimental extensions
2723
// CHECK-EMPTY:
28-
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
24+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13-
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1413
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1514
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1615
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@@ -19,11 +18,8 @@
1918
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
2019
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
2120
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22-
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23-
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24-
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2521
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2622
// CHECK-EMPTY:
2723
// CHECK-NEXT: Experimental extensions
2824
// CHECK-EMPTY:
29-
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
25+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,15 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13-
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1413
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1514
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1615
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
1716
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
1817
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
1918
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
2019
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21-
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22-
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23-
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2420
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2521
// CHECK-EMPTY:
2622
// CHECK-NEXT: Experimental extensions
2723
// CHECK-EMPTY:
28-
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
24+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -703,8 +703,6 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
703703
FeatureStdExtF,
704704
FeatureStdExtD,
705705
FeatureStdExtC,
706-
FeatureStdExtB,
707-
FeatureStdExtZbc,
708706
FeatureVendorXAndesPerf]>;
709707

710708
def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
@@ -718,8 +716,6 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
718716
FeatureStdExtF,
719717
FeatureStdExtD,
720718
FeatureStdExtC,
721-
FeatureStdExtB,
722-
FeatureStdExtZbc,
723719
FeatureVendorXAndesPerf]>;
724720

725721
defvar Andes45TuneFeatures = [TuneAndes45,
@@ -741,7 +737,6 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45",
741737
FeatureStdExtF,
742738
FeatureStdExtD,
743739
FeatureStdExtC,
744-
FeatureStdExtB,
745740
FeatureVendorXAndesPerf],
746741
Andes45TuneFeatures>;
747742

@@ -756,7 +751,6 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
756751
FeatureStdExtF,
757752
FeatureStdExtD,
758753
FeatureStdExtC,
759-
FeatureStdExtB,
760754
FeatureVendorXAndesPerf],
761755
Andes45TuneFeatures>;
762756

@@ -771,7 +765,6 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45",
771765
FeatureStdExtF,
772766
FeatureStdExtD,
773767
FeatureStdExtC,
774-
FeatureStdExtB,
775768
FeatureVendorXAndesPerf],
776769
Andes45TuneFeatures>;
777770

@@ -786,6 +779,5 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
786779
FeatureStdExtF,
787780
FeatureStdExtD,
788781
FeatureStdExtC,
789-
FeatureStdExtB,
790782
FeatureVendorXAndesPerf],
791783
Andes45TuneFeatures>;

‎llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2-
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+zbc -timeline -iterations=1 < %s | FileCheck %s
2+
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s
33

44
# Two ALUs without dependency can be dispatched in the same cycle.
55
add a0, a0, a0

0 commit comments

Comments
 (0)