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[X86] vector-compress.ll - add nounwind attoribute to remove cfi noise
1 parent 226a9d7 commit 24df8f5

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-58
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‎llvm/test/CodeGen/X86/vector-compress.ll

Lines changed: 33 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; RUN: llc -mtriple=x86_64 -mattr=+avx512f < %s | FileCheck %s --check-prefixes=CHECK,AVX512F
44
; RUN: llc -mtriple=x86_64 -mattr=+avx512f,+avx512vl,+avx512vbmi2 < %s | FileCheck %s --check-prefixes=CHECK,AVX512VL
55

6-
define <4 x i32> @test_compress_v4i32(<4 x i32> %vec, <4 x i1> %mask, <4 x i32> %passthru) {
6+
define <4 x i32> @test_compress_v4i32(<4 x i32> %vec, <4 x i1> %mask, <4 x i32> %passthru) nounwind {
77
; AVX2-LABEL: test_compress_v4i32:
88
; AVX2: # %bb.0:
99
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
@@ -64,7 +64,7 @@ define <4 x i32> @test_compress_v4i32(<4 x i32> %vec, <4 x i1> %mask, <4 x i32>
6464
ret <4 x i32> %out
6565
}
6666

67-
define <4 x float> @test_compress_v4f32(<4 x float> %vec, <4 x i1> %mask, <4 x float> %passthru) {
67+
define <4 x float> @test_compress_v4f32(<4 x float> %vec, <4 x i1> %mask, <4 x float> %passthru) nounwind {
6868
; AVX2-LABEL: test_compress_v4f32:
6969
; AVX2: # %bb.0:
7070
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
@@ -129,7 +129,7 @@ define <4 x float> @test_compress_v4f32(<4 x float> %vec, <4 x i1> %mask, <4 x f
129129
ret <4 x float> %out
130130
}
131131

132-
define <2 x i64> @test_compress_v2i64(<2 x i64> %vec, <2 x i1> %mask, <2 x i64> %passthru) {
132+
define <2 x i64> @test_compress_v2i64(<2 x i64> %vec, <2 x i1> %mask, <2 x i64> %passthru) nounwind {
133133
; AVX2-LABEL: test_compress_v2i64:
134134
; AVX2: # %bb.0:
135135
; AVX2-NEXT: vpsllq $63, %xmm1, %xmm1
@@ -181,7 +181,7 @@ define <2 x i64> @test_compress_v2i64(<2 x i64> %vec, <2 x i1> %mask, <2 x i64>
181181
ret <2 x i64> %out
182182
}
183183

184-
define <2 x double> @test_compress_v2f64(<2 x double> %vec, <2 x i1> %mask, <2 x double> %passthru) {
184+
define <2 x double> @test_compress_v2f64(<2 x double> %vec, <2 x i1> %mask, <2 x double> %passthru) nounwind {
185185
; AVX2-LABEL: test_compress_v2f64:
186186
; AVX2: # %bb.0:
187187
; AVX2-NEXT: vpsllq $63, %xmm1, %xmm1
@@ -236,18 +236,14 @@ define <2 x double> @test_compress_v2f64(<2 x double> %vec, <2 x i1> %mask, <2 x
236236
ret <2 x double> %out
237237
}
238238

239-
define <8 x i32> @test_compress_v8i32(<8 x i32> %vec, <8 x i1> %mask, <8 x i32> %passthru) {
239+
define <8 x i32> @test_compress_v8i32(<8 x i32> %vec, <8 x i1> %mask, <8 x i32> %passthru) nounwind {
240240
; AVX2-LABEL: test_compress_v8i32:
241241
; AVX2: # %bb.0:
242242
; AVX2-NEXT: pushq %rbp
243-
; AVX2-NEXT: .cfi_def_cfa_offset 16
244-
; AVX2-NEXT: .cfi_offset %rbp, -16
245243
; AVX2-NEXT: movq %rsp, %rbp
246-
; AVX2-NEXT: .cfi_def_cfa_register %rbp
247244
; AVX2-NEXT: pushq %rbx
248245
; AVX2-NEXT: andq $-32, %rsp
249246
; AVX2-NEXT: subq $64, %rsp
250-
; AVX2-NEXT: .cfi_offset %rbx, -24
251247
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
252248
; AVX2-NEXT: vpslld $31, %ymm1, %ymm1
253249
; AVX2-NEXT: vpsrad $31, %ymm1, %ymm3
@@ -315,7 +311,6 @@ define <8 x i32> @test_compress_v8i32(<8 x i32> %vec, <8 x i1> %mask, <8 x i32>
315311
; AVX2-NEXT: leaq -8(%rbp), %rsp
316312
; AVX2-NEXT: popq %rbx
317313
; AVX2-NEXT: popq %rbp
318-
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
319314
; AVX2-NEXT: retq
320315
;
321316
; AVX512F-LABEL: test_compress_v8i32:
@@ -340,14 +335,11 @@ define <8 x i32> @test_compress_v8i32(<8 x i32> %vec, <8 x i1> %mask, <8 x i32>
340335
ret <8 x i32> %out
341336
}
342337

343-
define <8 x float> @test_compress_v8f32(<8 x float> %vec, <8 x i1> %mask, <8 x float> %passthru) {
338+
define <8 x float> @test_compress_v8f32(<8 x float> %vec, <8 x i1> %mask, <8 x float> %passthru) nounwind {
344339
; AVX2-LABEL: test_compress_v8f32:
345340
; AVX2: # %bb.0:
346341
; AVX2-NEXT: pushq %rbp
347-
; AVX2-NEXT: .cfi_def_cfa_offset 16
348-
; AVX2-NEXT: .cfi_offset %rbp, -16
349342
; AVX2-NEXT: movq %rsp, %rbp
350-
; AVX2-NEXT: .cfi_def_cfa_register %rbp
351343
; AVX2-NEXT: andq $-32, %rsp
352344
; AVX2-NEXT: subq $64, %rsp
353345
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
@@ -424,7 +416,6 @@ define <8 x float> @test_compress_v8f32(<8 x float> %vec, <8 x i1> %mask, <8 x f
424416
; AVX2-NEXT: vmovaps (%rsp), %ymm0
425417
; AVX2-NEXT: movq %rbp, %rsp
426418
; AVX2-NEXT: popq %rbp
427-
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
428419
; AVX2-NEXT: retq
429420
;
430421
; AVX512F-LABEL: test_compress_v8f32:
@@ -449,14 +440,11 @@ define <8 x float> @test_compress_v8f32(<8 x float> %vec, <8 x i1> %mask, <8 x f
449440
ret <8 x float> %out
450441
}
451442

452-
define <4 x i64> @test_compress_v4i64(<4 x i64> %vec, <4 x i1> %mask, <4 x i64> %passthru) {
443+
define <4 x i64> @test_compress_v4i64(<4 x i64> %vec, <4 x i1> %mask, <4 x i64> %passthru) nounwind {
453444
; AVX2-LABEL: test_compress_v4i64:
454445
; AVX2: # %bb.0:
455446
; AVX2-NEXT: pushq %rbp
456-
; AVX2-NEXT: .cfi_def_cfa_offset 16
457-
; AVX2-NEXT: .cfi_offset %rbp, -16
458447
; AVX2-NEXT: movq %rsp, %rbp
459-
; AVX2-NEXT: .cfi_def_cfa_register %rbp
460448
; AVX2-NEXT: andq $-32, %rsp
461449
; AVX2-NEXT: subq $64, %rsp
462450
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
@@ -499,7 +487,6 @@ define <4 x i64> @test_compress_v4i64(<4 x i64> %vec, <4 x i1> %mask, <4 x i64>
499487
; AVX2-NEXT: vmovaps (%rsp), %ymm0
500488
; AVX2-NEXT: movq %rbp, %rsp
501489
; AVX2-NEXT: popq %rbp
502-
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
503490
; AVX2-NEXT: retq
504491
;
505492
; AVX512F-LABEL: test_compress_v4i64:
@@ -525,7 +512,7 @@ define <4 x i64> @test_compress_v4i64(<4 x i64> %vec, <4 x i1> %mask, <4 x i64>
525512
ret <4 x i64> %out
526513
}
527514

528-
define <4 x double> @test_compress_v4f64(<4 x double> %vec, <4 x i1> %mask, <4 x double> %passthru) {
515+
define <4 x double> @test_compress_v4f64(<4 x double> %vec, <4 x i1> %mask, <4 x double> %passthru) nounwind {
529516
; AVX512F-LABEL: test_compress_v4f64:
530517
; AVX512F: # %bb.0:
531518
; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
@@ -549,7 +536,7 @@ define <4 x double> @test_compress_v4f64(<4 x double> %vec, <4 x i1> %mask, <4 x
549536
ret <4 x double> %out
550537
}
551538

552-
define <16 x i32> @test_compress_v16i32(<16 x i32> %vec, <16 x i1> %mask, <16 x i32> %passthru) {
539+
define <16 x i32> @test_compress_v16i32(<16 x i32> %vec, <16 x i1> %mask, <16 x i32> %passthru) nounwind {
553540
; AVX512F-LABEL: test_compress_v16i32:
554541
; AVX512F: # %bb.0:
555542
; AVX512F-NEXT: vpmovsxbd %xmm1, %zmm1
@@ -570,7 +557,7 @@ define <16 x i32> @test_compress_v16i32(<16 x i32> %vec, <16 x i1> %mask, <16 x
570557
ret <16 x i32> %out
571558
}
572559

573-
define <16 x float> @test_compress_v16f32(<16 x float> %vec, <16 x i1> %mask, <16 x float> %passthru) {
560+
define <16 x float> @test_compress_v16f32(<16 x float> %vec, <16 x i1> %mask, <16 x float> %passthru) nounwind {
574561
; AVX512F-LABEL: test_compress_v16f32:
575562
; AVX512F: # %bb.0:
576563
; AVX512F-NEXT: vpmovsxbd %xmm1, %zmm1
@@ -591,7 +578,7 @@ define <16 x float> @test_compress_v16f32(<16 x float> %vec, <16 x i1> %mask, <1
591578
ret <16 x float> %out
592579
}
593580

594-
define <8 x i64> @test_compress_v8i64(<8 x i64> %vec, <8 x i1> %mask, <8 x i64> %passthru) {
581+
define <8 x i64> @test_compress_v8i64(<8 x i64> %vec, <8 x i1> %mask, <8 x i64> %passthru) nounwind {
595582
; AVX512F-LABEL: test_compress_v8i64:
596583
; AVX512F: # %bb.0:
597584
; AVX512F-NEXT: vpmovsxwq %xmm1, %zmm1
@@ -612,7 +599,7 @@ define <8 x i64> @test_compress_v8i64(<8 x i64> %vec, <8 x i1> %mask, <8 x i64>
612599
ret <8 x i64> %out
613600
}
614601

615-
define <8 x double> @test_compress_v8f64(<8 x double> %vec, <8 x i1> %mask, <8 x double> %passthru) {
602+
define <8 x double> @test_compress_v8f64(<8 x double> %vec, <8 x i1> %mask, <8 x double> %passthru) nounwind {
616603
; AVX512F-LABEL: test_compress_v8f64:
617604
; AVX512F: # %bb.0:
618605
; AVX512F-NEXT: vpmovsxwq %xmm1, %zmm1
@@ -633,7 +620,7 @@ define <8 x double> @test_compress_v8f64(<8 x double> %vec, <8 x i1> %mask, <8 x
633620
ret <8 x double> %out
634621
}
635622

636-
define <16 x i8> @test_compress_v16i8(<16 x i8> %vec, <16 x i1> %mask, <16 x i8> %passthru) {
623+
define <16 x i8> @test_compress_v16i8(<16 x i8> %vec, <16 x i1> %mask, <16 x i8> %passthru) nounwind {
637624
; AVX512F-LABEL: test_compress_v16i8:
638625
; AVX512F: # %bb.0:
639626
; AVX512F-NEXT: vpmovsxbd %xmm1, %zmm1
@@ -657,7 +644,7 @@ define <16 x i8> @test_compress_v16i8(<16 x i8> %vec, <16 x i1> %mask, <16 x i8>
657644
ret <16 x i8> %out
658645
}
659646

660-
define <8 x i16> @test_compress_v8i16(<8 x i16> %vec, <8 x i1> %mask, <8 x i16> %passthru) {
647+
define <8 x i16> @test_compress_v8i16(<8 x i16> %vec, <8 x i1> %mask, <8 x i16> %passthru) nounwind {
661648
; AVX512F-LABEL: test_compress_v8i16:
662649
; AVX512F: # %bb.0:
663650
; AVX512F-NEXT: vpmovsxwq %xmm1, %zmm1
@@ -681,14 +668,11 @@ define <8 x i16> @test_compress_v8i16(<8 x i16> %vec, <8 x i1> %mask, <8 x i16>
681668
ret <8 x i16> %out
682669
}
683670

684-
define <32 x i8> @test_compress_v32i8(<32 x i8> %vec, <32 x i1> %mask, <32 x i8> %passthru) {
671+
define <32 x i8> @test_compress_v32i8(<32 x i8> %vec, <32 x i1> %mask, <32 x i8> %passthru) nounwind {
685672
; AVX512F-LABEL: test_compress_v32i8:
686673
; AVX512F: # %bb.0:
687674
; AVX512F-NEXT: pushq %rbp
688-
; AVX512F-NEXT: .cfi_def_cfa_offset 16
689-
; AVX512F-NEXT: .cfi_offset %rbp, -16
690675
; AVX512F-NEXT: movq %rsp, %rbp
691-
; AVX512F-NEXT: .cfi_def_cfa_register %rbp
692676
; AVX512F-NEXT: andq $-32, %rsp
693677
; AVX512F-NEXT: subq $64, %rsp
694678
; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm3
@@ -719,7 +703,6 @@ define <32 x i8> @test_compress_v32i8(<32 x i8> %vec, <32 x i1> %mask, <32 x i8>
719703
; AVX512F-NEXT: vpblendvb %ymm0, (%rsp), %ymm2, %ymm0
720704
; AVX512F-NEXT: movq %rbp, %rsp
721705
; AVX512F-NEXT: popq %rbp
722-
; AVX512F-NEXT: .cfi_def_cfa %rsp, 8
723706
; AVX512F-NEXT: retq
724707
;
725708
; AVX512VL-LABEL: test_compress_v32i8:
@@ -733,7 +716,7 @@ define <32 x i8> @test_compress_v32i8(<32 x i8> %vec, <32 x i1> %mask, <32 x i8>
733716
ret <32 x i8> %out
734717
}
735718

736-
define <16 x i16> @test_compress_v16i16(<16 x i16> %vec, <16 x i1> %mask, <16 x i16> %passthru) {
719+
define <16 x i16> @test_compress_v16i16(<16 x i16> %vec, <16 x i1> %mask, <16 x i16> %passthru) nounwind {
737720
; AVX512F-LABEL: test_compress_v16i16:
738721
; AVX512F: # %bb.0:
739722
; AVX512F-NEXT: vpmovsxbd %xmm1, %zmm1
@@ -756,7 +739,7 @@ define <16 x i16> @test_compress_v16i16(<16 x i16> %vec, <16 x i1> %mask, <16 x
756739
ret <16 x i16> %out
757740
}
758741

759-
define <64 x i8> @test_compress_v64i8(<64 x i8> %vec, <64 x i1> %mask, <64 x i8> %passthru) {
742+
define <64 x i8> @test_compress_v64i8(<64 x i8> %vec, <64 x i1> %mask, <64 x i8> %passthru) nounwind {
760743
; AVX512VL-LABEL: test_compress_v64i8:
761744
; AVX512VL: # %bb.0:
762745
; AVX512VL-NEXT: vpsllw $7, %zmm1, %zmm1
@@ -768,14 +751,11 @@ define <64 x i8> @test_compress_v64i8(<64 x i8> %vec, <64 x i1> %mask, <64 x i8>
768751
ret <64 x i8> %out
769752
}
770753

771-
define <32 x i16> @test_compress_v32i16(<32 x i16> %vec, <32 x i1> %mask, <32 x i16> %passthru) {
754+
define <32 x i16> @test_compress_v32i16(<32 x i16> %vec, <32 x i1> %mask, <32 x i16> %passthru) nounwind {
772755
; AVX512F-LABEL: test_compress_v32i16:
773756
; AVX512F: # %bb.0:
774757
; AVX512F-NEXT: pushq %rbp
775-
; AVX512F-NEXT: .cfi_def_cfa_offset 16
776-
; AVX512F-NEXT: .cfi_offset %rbp, -16
777758
; AVX512F-NEXT: movq %rsp, %rbp
778-
; AVX512F-NEXT: .cfi_def_cfa_register %rbp
779759
; AVX512F-NEXT: andq $-64, %rsp
780760
; AVX512F-NEXT: subq $128, %rsp
781761
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm3 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
@@ -814,7 +794,6 @@ define <32 x i16> @test_compress_v32i16(<32 x i16> %vec, <32 x i1> %mask, <32 x
814794
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
815795
; AVX512F-NEXT: movq %rbp, %rsp
816796
; AVX512F-NEXT: popq %rbp
817-
; AVX512F-NEXT: .cfi_def_cfa %rsp, 8
818797
; AVX512F-NEXT: retq
819798
;
820799
; AVX512VL-LABEL: test_compress_v32i16:
@@ -828,14 +807,11 @@ define <32 x i16> @test_compress_v32i16(<32 x i16> %vec, <32 x i1> %mask, <32 x
828807
ret <32 x i16> %out
829808
}
830809

831-
define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i32> %passthru) {
810+
define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i32> %passthru) nounwind {
832811
; AVX512VL-LABEL: test_compress_large:
833812
; AVX512VL: # %bb.0:
834813
; AVX512VL-NEXT: pushq %rbp
835-
; AVX512VL-NEXT: .cfi_def_cfa_offset 16
836-
; AVX512VL-NEXT: .cfi_offset %rbp, -16
837814
; AVX512VL-NEXT: movq %rsp, %rbp
838-
; AVX512VL-NEXT: .cfi_def_cfa_register %rbp
839815
; AVX512VL-NEXT: andq $-64, %rsp
840816
; AVX512VL-NEXT: subq $576, %rsp # imm = 0x240
841817
; AVX512VL-NEXT: vpsllw $7, %zmm0, %zmm0
@@ -896,13 +872,12 @@ define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i
896872
; AVX512VL-NEXT: vmovaps {{[0-9]+}}(%rsp), %zmm3
897873
; AVX512VL-NEXT: movq %rbp, %rsp
898874
; AVX512VL-NEXT: popq %rbp
899-
; AVX512VL-NEXT: .cfi_def_cfa %rsp, 8
900875
; AVX512VL-NEXT: retq
901876
%out = call <64 x i32> @llvm.experimental.vector.compress(<64 x i32> %vec, <64 x i1> %mask, <64 x i32> undef)
902877
ret <64 x i32> %out
903878
}
904879

905-
define <4 x i32> @test_compress_all_const() {
880+
define <4 x i32> @test_compress_all_const() nounwind {
906881
; AVX2-LABEL: test_compress_all_const:
907882
; AVX2: # %bb.0:
908883
; AVX2-NEXT: vmovsd {{.*#+}} xmm0 = [5,9,0,0]
@@ -923,7 +898,7 @@ define <4 x i32> @test_compress_all_const() {
923898
ret <4 x i32> %out
924899
}
925900

926-
define <4 x i32> @test_compress_const_mask(<4 x i32> %vec) {
901+
define <4 x i32> @test_compress_const_mask(<4 x i32> %vec) nounwind {
927902
; CHECK-LABEL: test_compress_const_mask:
928903
; CHECK: # %bb.0:
929904
; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3,2,3]
@@ -932,7 +907,7 @@ define <4 x i32> @test_compress_const_mask(<4 x i32> %vec) {
932907
ret <4 x i32> %out
933908
}
934909

935-
define <4 x i32> @test_compress_const_mask_passthrough(<4 x i32> %vec, <4 x i32> %passthru) {
910+
define <4 x i32> @test_compress_const_mask_passthrough(<4 x i32> %vec, <4 x i32> %passthru) nounwind {
936911
; CHECK-LABEL: test_compress_const_mask_passthrough:
937912
; CHECK: # %bb.0:
938913
; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[2,3]
@@ -941,7 +916,7 @@ define <4 x i32> @test_compress_const_mask_passthrough(<4 x i32> %vec, <4 x i32>
941916
ret <4 x i32> %out
942917
}
943918

944-
define <4 x i32> @test_compress_const_mask_const_passthrough(<4 x i32> %vec) {
919+
define <4 x i32> @test_compress_const_mask_const_passthrough(<4 x i32> %vec) nounwind {
945920
; CHECK-LABEL: test_compress_const_mask_const_passthrough:
946921
; CHECK: # %bb.0:
947922
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
@@ -956,45 +931,45 @@ define <4 x i32> @test_compress_const_mask_const_passthrough(<4 x i32> %vec) {
956931

957932
; We pass a placeholder value for the const_mask* tests to check that they are converted to a no-op by simply copying
958933
; the second vector input register to the return register or doing nothing.
959-
define <4 x i32> @test_compress_const_splat1_mask(<4 x i32> %ignore, <4 x i32> %vec) {
934+
define <4 x i32> @test_compress_const_splat1_mask(<4 x i32> %ignore, <4 x i32> %vec) nounwind {
960935
; CHECK-LABEL: test_compress_const_splat1_mask:
961936
; CHECK: # %bb.0:
962937
; CHECK-NEXT: vmovaps %xmm1, %xmm0
963938
; CHECK-NEXT: retq
964939
%out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 -1), <4 x i32> undef)
965940
ret <4 x i32> %out
966941
}
967-
define <4 x i32> @test_compress_const_splat0_mask(<4 x i32> %ignore, <4 x i32> %vec) {
942+
define <4 x i32> @test_compress_const_splat0_mask(<4 x i32> %ignore, <4 x i32> %vec) nounwind {
968943
; CHECK-LABEL: test_compress_const_splat0_mask:
969944
; CHECK: # %bb.0:
970945
; CHECK-NEXT: retq
971946
%out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 0), <4 x i32> undef)
972947
ret <4 x i32> %out
973948
}
974-
define <4 x i32> @test_compress_undef_mask(<4 x i32> %ignore, <4 x i32> %vec) {
949+
define <4 x i32> @test_compress_undef_mask(<4 x i32> %ignore, <4 x i32> %vec) nounwind {
975950
; CHECK-LABEL: test_compress_undef_mask:
976951
; CHECK: # %bb.0:
977952
; CHECK-NEXT: retq
978953
%out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> undef, <4 x i32> undef)
979954
ret <4 x i32> %out
980955
}
981-
define <4 x i32> @test_compress_const_splat0_mask_with_passthru(<4 x i32> %ignore, <4 x i32> %vec, <4 x i32> %passthru) {
956+
define <4 x i32> @test_compress_const_splat0_mask_with_passthru(<4 x i32> %ignore, <4 x i32> %vec, <4 x i32> %passthru) nounwind {
982957
; CHECK-LABEL: test_compress_const_splat0_mask_with_passthru:
983958
; CHECK: # %bb.0:
984959
; CHECK-NEXT: vmovaps %xmm2, %xmm0
985960
; CHECK-NEXT: retq
986961
%out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 0), <4 x i32> %passthru)
987962
ret <4 x i32> %out
988963
}
989-
define <4 x i32> @test_compress_const_splat0_mask_without_passthru(<4 x i32> %ignore, <4 x i32> %vec) {
964+
define <4 x i32> @test_compress_const_splat0_mask_without_passthru(<4 x i32> %ignore, <4 x i32> %vec) nounwind {
990965
; CHECK-LABEL: test_compress_const_splat0_mask_without_passthru:
991966
; CHECK: # %bb.0:
992967
; CHECK-NEXT: retq
993968
%out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 0), <4 x i32> undef)
994969
ret <4 x i32> %out
995970
}
996971

997-
define <4 x i8> @test_compress_small(<4 x i8> %vec, <4 x i1> %mask) {
972+
define <4 x i8> @test_compress_small(<4 x i8> %vec, <4 x i1> %mask) nounwind {
998973
; AVX512F-LABEL: test_compress_small:
999974
; AVX512F: # %bb.0:
1000975
; AVX512F-NEXT: vpslld $31, %xmm1, %xmm1
@@ -1017,7 +992,7 @@ define <4 x i8> @test_compress_small(<4 x i8> %vec, <4 x i1> %mask) {
1017992
ret <4 x i8> %out
1018993
}
1019994

1020-
define <4 x i4> @test_compress_illegal_element_type(<4 x i4> %vec, <4 x i1> %mask) {
995+
define <4 x i4> @test_compress_illegal_element_type(<4 x i4> %vec, <4 x i1> %mask) nounwind {
1021996
; AVX2-LABEL: test_compress_illegal_element_type:
1022997
; AVX2: # %bb.0:
1023998
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
@@ -1059,7 +1034,7 @@ define <4 x i4> @test_compress_illegal_element_type(<4 x i4> %vec, <4 x i1> %mas
10591034
ret <4 x i4> %out
10601035
}
10611036

1062-
define <3 x i32> @test_compress_narrow(<3 x i32> %vec, <3 x i1> %mask) {
1037+
define <3 x i32> @test_compress_narrow(<3 x i32> %vec, <3 x i1> %mask) nounwind {
10631038
; AVX2-LABEL: test_compress_narrow:
10641039
; AVX2: # %bb.0:
10651040
; AVX2-NEXT: vmovd %edi, %xmm1
@@ -1132,7 +1107,7 @@ define <3 x i32> @test_compress_narrow(<3 x i32> %vec, <3 x i1> %mask) {
11321107
ret <3 x i32> %out
11331108
}
11341109

1135-
define <3 x i3> @test_compress_narrow_illegal_element_type(<3 x i3> %vec, <3 x i1> %mask) {
1110+
define <3 x i3> @test_compress_narrow_illegal_element_type(<3 x i3> %vec, <3 x i1> %mask) nounwind {
11361111
; AVX2-LABEL: test_compress_narrow_illegal_element_type:
11371112
; AVX2: # %bb.0:
11381113
; AVX2-NEXT: vmovd %ecx, %xmm0
@@ -1222,7 +1197,7 @@ define <3 x i3> @test_compress_narrow_illegal_element_type(<3 x i3> %vec, <3 x i
12221197
ret <3 x i3> %out
12231198
}
12241199

1225-
define <4 x i32> @test_compress_v4i32_zero_passthru(<4 x i32> %vec, <4 x i1> %mask) {
1200+
define <4 x i32> @test_compress_v4i32_zero_passthru(<4 x i32> %vec, <4 x i1> %mask) nounwind {
12261201
; AVX2-LABEL: test_compress_v4i32_zero_passthru:
12271202
; AVX2: # %bb.0:
12281203
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1

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