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[VectorCombine][X86] shuffle-of-binops.ll - split off foldShuffleOfBinops tests from shuffle.ll
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‎llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=SSE2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=AVX2 | FileCheck %s --check-prefixes=CHECK,AVX
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declare void @use(<4 x i32>)
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; Shuffle is much cheaper than fdiv. FMF are intersected.
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define <4 x float> @shuf_fdiv_v4f32_yy(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; CHECK-LABEL: define <4 x float> @shuf_fdiv_v4f32_yy(
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; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[X]], <4 x float> [[Z]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> poison, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
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; CHECK-NEXT: [[R:%.*]] = fdiv arcp <4 x float> [[TMP2]], [[TMP3]]
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; CHECK-NEXT: ret <4 x float> [[R]]
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;
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%b0 = fdiv fast <4 x float> %x, %y
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%b1 = fdiv arcp <4 x float> %z, %y
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%r = shufflevector <4 x float> %b0, <4 x float> %b1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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ret <4 x float> %r
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}
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; Common operand is op0 of the binops.
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define <4 x i32> @shuf_add_v4i32_xx(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
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; CHECK-LABEL: define <4 x i32> @shuf_add_v4i32_xx(
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; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <4 x i32> <i32 poison, i32 poison, i32 2, i32 0>
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; CHECK-NEXT: [[R1:%.*]] = shufflevector <4 x i32> [[Y]], <4 x i32> [[Z]], <4 x i32> <i32 poison, i32 poison, i32 6, i32 0>
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; CHECK-NEXT: [[R2:%.*]] = add <4 x i32> [[TMP1]], [[R1]]
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; CHECK-NEXT: ret <4 x i32> [[R2]]
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;
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%b0 = add <4 x i32> %x, %y
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%b1 = add <4 x i32> %x, %z
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%r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 poison, i32 poison, i32 6, i32 0>
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ret <4 x i32> %r
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}
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; For commutative instructions, common operand may be swapped.
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define <4 x float> @shuf_fmul_v4f32_xx_swap(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; CHECK-LABEL: define <4 x float> @shuf_fmul_v4f32_xx_swap(
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; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> [[Z]], <4 x i32> <i32 0, i32 3, i32 4, i32 7>
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[X]], <4 x float> poison, <4 x i32> <i32 0, i32 3, i32 0, i32 3>
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; CHECK-NEXT: [[R:%.*]] = fmul <4 x float> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret <4 x float> [[R]]
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;
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%b0 = fmul <4 x float> %x, %y
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%b1 = fmul <4 x float> %z, %x
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%r = shufflevector <4 x float> %b0, <4 x float> %b1, <4 x i32> <i32 0, i32 3, i32 4, i32 7>
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ret <4 x float> %r
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}
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; For commutative instructions, common operand may be swapped.
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define <2 x i64> @shuf_and_v2i64_yy_swap(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
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; CHECK-LABEL: define <2 x i64> @shuf_and_v2i64_yy_swap(
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; CHECK-SAME: <2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], <2 x i64> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[Y]], <2 x i64> poison, <2 x i32> <i32 1, i32 0>
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[X]], <2 x i64> [[Z]], <2 x i32> <i32 3, i32 0>
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; CHECK-NEXT: [[R:%.*]] = and <2 x i64> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret <2 x i64> [[R]]
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;
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%b0 = and <2 x i64> %x, %y
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%b1 = and <2 x i64> %y, %z
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%r = shufflevector <2 x i64> %b0, <2 x i64> %b1, <2 x i32> <i32 3, i32 0>
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ret <2 x i64> %r
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}
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; non-commutative binop, but common op0
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define <4 x i32> @shuf_shl_v4i32_xx(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
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; CHECK-LABEL: define <4 x i32> @shuf_shl_v4i32_xx(
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; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <4 x i32> <i32 3, i32 1, i32 1, i32 2>
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[Y]], <4 x i32> [[Z]], <4 x i32> <i32 3, i32 1, i32 1, i32 6>
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; CHECK-NEXT: [[R:%.*]] = shl <4 x i32> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret <4 x i32> [[R]]
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;
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%b0 = shl <4 x i32> %x, %y
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%b1 = shl <4 x i32> %x, %z
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%r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 3, i32 1, i32 1, i32 6>
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ret <4 x i32> %r
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}
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; negative test - common operand, but not commutable
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define <4 x i32> @shuf_shl_v4i32_xx_swap(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
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; CHECK-LABEL: define <4 x i32> @shuf_shl_v4i32_xx_swap(
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; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[B0:%.*]] = shl <4 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[B1:%.*]] = shl <4 x i32> [[Z]], [[X]]
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; CHECK-NEXT: [[R1:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 3, i32 2, i32 2, i32 5>
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; CHECK-NEXT: ret <4 x i32> [[R1]]
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;
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%b0 = shl <4 x i32> %x, %y
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%b1 = shl <4 x i32> %z, %x
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%r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 3, i32 2, i32 2, i32 5>
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ret <4 x i32> %r
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}
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; negative test - mismatched opcodes
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define <2 x i64> @shuf_sub_add_v2i64_yy(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
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; CHECK-LABEL: define <2 x i64> @shuf_sub_add_v2i64_yy(
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; CHECK-SAME: <2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], <2 x i64> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[B0:%.*]] = sub <2 x i64> [[X]], [[Y]]
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; CHECK-NEXT: [[B1:%.*]] = add <2 x i64> [[Z]], [[Y]]
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; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i64> [[B0]], <2 x i64> [[B1]], <2 x i32> <i32 3, i32 0>
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; CHECK-NEXT: ret <2 x i64> [[R]]
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;
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%b0 = sub <2 x i64> %x, %y
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%b1 = add <2 x i64> %z, %y
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%r = shufflevector <2 x i64> %b0, <2 x i64> %b1, <2 x i32> <i32 3, i32 0>
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ret <2 x i64> %r
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}
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; negative test - type change via shuffle
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define <8 x float> @shuf_fmul_v4f32_xx_type(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; CHECK-LABEL: define <8 x float> @shuf_fmul_v4f32_xx_type(
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; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[B0:%.*]] = fmul <4 x float> [[X]], [[Y]]
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; CHECK-NEXT: [[B1:%.*]] = fmul <4 x float> [[Z]], [[X]]
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; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <8 x i32> <i32 0, i32 3, i32 4, i32 7, i32 0, i32 1, i32 1, i32 6>
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; CHECK-NEXT: ret <8 x float> [[R]]
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;
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%b0 = fmul <4 x float> %x, %y
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%b1 = fmul <4 x float> %z, %x
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%r = shufflevector <4 x float> %b0, <4 x float> %b1, <8 x i32> <i32 0, i32 3, i32 4, i32 7, i32 0, i32 1, i32 1, i32 6>
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ret <8 x float> %r
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}
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; negative test - uses
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define <4 x i32> @shuf_lshr_v4i32_yy_use1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
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; CHECK-LABEL: define <4 x i32> @shuf_lshr_v4i32_yy_use1(
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; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[B0:%.*]] = lshr <4 x i32> [[X]], [[Y]]
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; CHECK-NEXT: call void @use(<4 x i32> [[B0]])
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; CHECK-NEXT: [[B1:%.*]] = lshr <4 x i32> [[Z]], [[Y]]
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; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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; CHECK-NEXT: ret <4 x i32> [[R]]
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;
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%b0 = lshr <4 x i32> %x, %y
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call void @use(<4 x i32> %b0)
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%b1 = lshr <4 x i32> %z, %y
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%r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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ret <4 x i32> %r
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}
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; negative test - uses
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define <4 x i32> @shuf_mul_v4i32_yy_use2(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
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; CHECK-LABEL: define <4 x i32> @shuf_mul_v4i32_yy_use2(
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; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[B0:%.*]] = mul <4 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[B1:%.*]] = mul <4 x i32> [[Z]], [[Y]]
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; CHECK-NEXT: call void @use(<4 x i32> [[B1]])
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; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[R]]
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;
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%b0 = mul <4 x i32> %x, %y
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%b1 = mul <4 x i32> %z, %y
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call void @use(<4 x i32> %b1)
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%r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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ret <4 x i32> %r
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}
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; negative test - must have matching operand
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define <4 x float> @shuf_fadd_v4f32_no_common_op(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
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; CHECK-LABEL: define <4 x float> @shuf_fadd_v4f32_no_common_op(
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; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]], <4 x float> [[W:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[B0:%.*]] = fadd <4 x float> [[X]], [[Y]]
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; CHECK-NEXT: [[B1:%.*]] = fadd <4 x float> [[Z]], [[W]]
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; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: ret <4 x float> [[R]]
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;
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%b0 = fadd <4 x float> %x, %y
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%b1 = fadd <4 x float> %z, %w
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%r = shufflevector <4 x float> %b0, <4 x float> %b1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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ret <4 x float> %r
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}
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; negative test - binops may be relatively cheap
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define <16 x i16> @shuf_and_v16i16_yy_expensive_shuf(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) {
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; CHECK-LABEL: define <16 x i16> @shuf_and_v16i16_yy_expensive_shuf(
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; CHECK-SAME: <16 x i16> [[X:%.*]], <16 x i16> [[Y:%.*]], <16 x i16> [[Z:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[B0:%.*]] = and <16 x i16> [[X]], [[Y]]
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; CHECK-NEXT: [[B1:%.*]] = and <16 x i16> [[Y]], [[Z]]
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; CHECK-NEXT: [[R:%.*]] = shufflevector <16 x i16> [[B0]], <16 x i16> [[B1]], <16 x i32> <i32 15, i32 22, i32 25, i32 13, i32 28, i32 0, i32 poison, i32 3, i32 0, i32 30, i32 3, i32 7, i32 9, i32 19, i32 2, i32 22>
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; CHECK-NEXT: ret <16 x i16> [[R]]
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;
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%b0 = and <16 x i16> %x, %y
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%b1 = and <16 x i16> %y, %z
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%r = shufflevector <16 x i16> %b0, <16 x i16> %b1, <16 x i32> <i32 15, i32 22, i32 25, i32 13, i32 28, i32 0, i32 poison, i32 3, i32 0, i32 30, i32 3, i32 7, i32 9, i32 19, i32 2, i32 22>
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ret <16 x i16> %r
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; AVX: {{.*}}
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; SSE: {{.*}}

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