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[NFC] [InstCombine] Modify and Added tests for select-of-bittest
Tests that begin with n in select-of-bittest are negative tests. However, n5 test is different from the intent of the test because bits in %t and %t2 are the same. This is probably a mistake, so corrected it. Also added tests for cases where the and/or/xor might be optimized if it is placed in the cond and truval of selectInst. proof : https://alive2.llvm.org/ce/z/A4PJ3E
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‎llvm/test/Transforms/InstCombine/select-of-bittest.ll

Lines changed: 210 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,214 @@
33

44
; https://bugs.llvm.org/show_bug.cgi?id=36950
55

6-
; These all should be just and+icmp, there should be no select.
6+
; ====================== AND =======================
7+
define i8 @src_and_bit(i8 %x, i8 %y) {
8+
; CHECK-LABEL: @src_and_bit(
9+
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 3
10+
; CHECK-NEXT: [[AND1:%.*]] = and i8 [[X]], 2
11+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 2
12+
; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i8 [[AND1]], i8 1
13+
; CHECK-NEXT: ret i8 [[COND]]
14+
;
15+
%and = and i8 %x, 3
16+
%and1 = and i8 %x, 2
17+
%and2 = and i8 %and, %x
18+
%cmp = icmp eq i8 %and2, 2
19+
%cond = select i1 %cmp, i8 %and1, i8 1
20+
ret i8 %cond
21+
}
22+
define <2 x i8> @src_and_bit_vec(<2 x i8> %x, <2 x i8> %y) {
23+
; CHECK-LABEL: @src_and_bit_vec(
24+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 3, i8 3>
25+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 2, i8 2>
26+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[AND]], <i8 2, i8 2>
27+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
28+
; CHECK-NEXT: ret <2 x i8> [[COND]]
29+
;
30+
%and = and <2 x i8> %x, <i8 3, i8 3>
31+
%and1 = and <2 x i8> %x, <i8 2, i8 2>
32+
%and2 = and <2 x i8> %and, %x
33+
%cmp = icmp eq <2 x i8> %and2, <i8 2, i8 2>
34+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8><i8 1, i8 1>
35+
ret <2 x i8> %cond
36+
}
37+
define <2 x i8> @src_and_bit_vec_poison(<2 x i8> %x, <2 x i8> %y) {
38+
; CHECK-LABEL: @src_and_bit_vec_poison(
39+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 poison, i8 3>
40+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 poison, i8 2>
41+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[AND]], <i8 2, i8 2>
42+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
43+
; CHECK-NEXT: ret <2 x i8> [[COND]]
44+
;
45+
%and = and <2 x i8> %x, <i8 poison, i8 3>
46+
%and1 = and <2 x i8> %x, <i8 poison, i8 2>
47+
%and2 = and <2 x i8> %and, %x
48+
%cmp = icmp eq <2 x i8> %and2, <i8 2, i8 2>
49+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8><i8 1, i8 1>
50+
ret <2 x i8> %cond
51+
}
52+
define <2 x i8> @src_and_bit_vec_poison2(<2 x i8> %x, <2 x i8> %y) {
53+
; CHECK-LABEL: @src_and_bit_vec_poison2(
54+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 poison, i8 3>
55+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 poison, i8 2>
56+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[AND]], <i8 2, i8 2>
57+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
58+
; CHECK-NEXT: ret <2 x i8> [[COND]]
59+
;
60+
%and = and <2 x i8> %x, <i8 poison, i8 3>
61+
%and1 = and <2 x i8> %x, <i8 poison, i8 2>
62+
%and2 = and <2 x i8> %and, %x
63+
%cmp = icmp eq <2 x i8> %and2, <i8 2, i8 2>
64+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8><i8 1, i8 1>
65+
ret <2 x i8> %cond
66+
}
67+
68+
; ====================== OR =======================
69+
define i8 @src_or_bit(i8 %x, i8 %y, i8 %z) {
70+
; CHECK-LABEL: @src_or_bit(
71+
; CHECK-NEXT: [[AND:%.*]] = and i8 [[Z:%.*]], 3
72+
; CHECK-NEXT: [[AND1:%.*]] = shl i8 [[Y:%.*]], 2
73+
; CHECK-NEXT: [[SHL:%.*]] = and i8 [[AND1]], 12
74+
; CHECK-NEXT: [[OR:%.*]] = or i8 [[SHL]], [[X:%.*]]
75+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], 3
76+
; CHECK-NEXT: [[OR2:%.*]] = or i8 [[AND]], [[X]]
77+
; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i8 [[OR2]], i8 1
78+
; CHECK-NEXT: ret i8 [[COND]]
79+
;
80+
%and = and i8 %z, 3
81+
%and1 = shl i8 %y, 2
82+
%shl = and i8 %and1, 12
83+
%or = or i8 %shl, %x
84+
%cmp = icmp eq i8 %or, 3
85+
%or2 = or i8 %and, %x
86+
%cond = select i1 %cmp, i8 %or2, i8 1
87+
ret i8 %cond
88+
}
89+
define <2 x i8> @src_or_bit_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
90+
; CHECK-LABEL: @src_or_bit_vec(
91+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Z:%.*]], <i8 3, i8 3>
92+
; CHECK-NEXT: [[AND1:%.*]] = shl <2 x i8> [[Y:%.*]], <i8 2, i8 2>
93+
; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[AND1]], <i8 12, i8 12>
94+
; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[SHL]], [[X:%.*]]
95+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[OR]], <i8 3, i8 3>
96+
; CHECK-NEXT: [[OR2:%.*]] = or <2 x i8> [[AND]], [[X]]
97+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[OR2]], <2 x i8> <i8 1, i8 1>
98+
; CHECK-NEXT: ret <2 x i8> [[COND]]
99+
;
100+
%and = and <2 x i8> %z, <i8 3, i8 3>
101+
%and1 = shl <2 x i8> %y, <i8 2, i8 2>
102+
%shl = and <2 x i8> %and1, <i8 12, i8 12>
103+
%or = or <2 x i8> %shl, %x
104+
%cmp = icmp eq <2 x i8> %or, <i8 3, i8 3>
105+
%or2 = or <2 x i8> %and, %x
106+
%cond = select <2x i1> %cmp, <2 x i8> %or2, <2 x i8> <i8 1, i8 1>
107+
ret <2 x i8> %cond
108+
}
109+
define <2 x i8> @src_or_bit_vec_poison(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
110+
; CHECK-LABEL: @src_or_bit_vec_poison(
111+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Z:%.*]], <i8 3, i8 poison>
112+
; CHECK-NEXT: [[AND1:%.*]] = shl <2 x i8> [[Y:%.*]], <i8 2, i8 poison>
113+
; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[AND1]], <i8 12, i8 poison>
114+
; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[SHL]], [[X:%.*]]
115+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[OR]], <i8 3, i8 3>
116+
; CHECK-NEXT: [[OR2:%.*]] = or <2 x i8> [[AND]], [[X]]
117+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[OR2]], <2 x i8> <i8 1, i8 1>
118+
; CHECK-NEXT: ret <2 x i8> [[COND]]
119+
;
120+
%and = and <2 x i8> %z, <i8 3, i8 poison>
121+
%and1 = shl <2 x i8> %y, <i8 2, i8 poison>
122+
%shl = and <2 x i8> %and1, <i8 12, i8 poison>
123+
%or = or <2 x i8> %shl, %x
124+
%cmp = icmp eq <2 x i8> %or, <i8 3, i8 3>
125+
%or2 = or <2 x i8> %and, %x
126+
%cond = select <2 x i1> %cmp, <2 x i8> %or2, <2 x i8> <i8 1, i8 1>
127+
ret <2 x i8> %cond
128+
}
129+
define <2 x i8> @src_or_bit_vec_poison2(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
130+
; CHECK-LABEL: @src_or_bit_vec_poison2(
131+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Z:%.*]], <i8 poison, i8 3>
132+
; CHECK-NEXT: [[AND1:%.*]] = shl <2 x i8> [[Y:%.*]], <i8 poison, i8 2>
133+
; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[AND1]], <i8 poison, i8 12>
134+
; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[SHL]], [[X:%.*]]
135+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[OR]], <i8 3, i8 3>
136+
; CHECK-NEXT: [[OR2:%.*]] = or <2 x i8> [[AND]], [[X]]
137+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[OR2]], <2 x i8> <i8 1, i8 1>
138+
; CHECK-NEXT: ret <2 x i8> [[COND]]
139+
;
140+
%and = and <2 x i8> %z, <i8 poison, i8 3>
141+
%and1 = shl <2 x i8> %y, <i8 poison, i8 2>
142+
%shl = and <2 x i8> %and1, <i8 poison, i8 12>
143+
%or = or <2 x i8> %shl, %x
144+
%cmp = icmp eq <2 x i8> %or, <i8 3, i8 3>
145+
%or2 = or <2 x i8> %and, %x
146+
%cond = select <2 x i1> %cmp, <2 x i8> %or2, <2 x i8> <i8 1, i8 1>
147+
ret <2 x i8> %cond
148+
}
149+
150+
define i8 @src_xor_bit(i8 %x, i8 %y) {
151+
; CHECK-LABEL: @src_xor_bit(
152+
; CHECK-NEXT: [[AND:%.*]] = and i8 [[Y:%.*]], 12
153+
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[AND]], [[X:%.*]]
154+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[XOR]], 3
155+
; CHECK-NEXT: [[AND1:%.*]] = and i8 [[X]], 3
156+
; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i8 [[AND1]], i8 1
157+
; CHECK-NEXT: ret i8 [[COND]]
158+
;
159+
%and = and i8 %y, 12
160+
%xor = xor i8 %and, %x
161+
%cmp = icmp eq i8 %xor, 3
162+
%and1 = and i8 %x, 3
163+
%cond = select i1 %cmp, i8 %and1, i8 1
164+
ret i8 %cond
165+
}
166+
define <2 x i8> @src_xor_bit_vec(<2 x i8> %x, <2 x i8> %y) {
167+
; CHECK-LABEL: @src_xor_bit_vec(
168+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Y:%.*]], <i8 12, i8 12>
169+
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i8> [[AND]], [[X:%.*]]
170+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[XOR]], <i8 3, i8 3>
171+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 3, i8 3>
172+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
173+
; CHECK-NEXT: ret <2 x i8> [[COND]]
174+
;
175+
%and = and <2 x i8> %y, <i8 12, i8 12>
176+
%xor = xor <2 x i8> %and, %x
177+
%cmp = icmp eq <2 x i8> %xor, <i8 3, i8 3>
178+
%and1 = and <2 x i8> %x, <i8 3, i8 3>
179+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8> <i8 1, i8 1>
180+
ret <2 x i8> %cond
181+
}
182+
define <2 x i8> @src_xor_bit_vec_poison(<2 x i8> %x, <2 x i8> %y) {
183+
; CHECK-LABEL: @src_xor_bit_vec_poison(
184+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Y:%.*]], <i8 poison, i8 12>
185+
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i8> [[AND]], [[X:%.*]]
186+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[XOR]], <i8 3, i8 3>
187+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 poison, i8 3>
188+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
189+
; CHECK-NEXT: ret <2 x i8> [[COND]]
190+
;
191+
%and = and <2 x i8> %y, <i8 poison, i8 12>
192+
%xor = xor <2 x i8> %and, %x
193+
%cmp = icmp eq <2 x i8> %xor, <i8 3, i8 3>
194+
%and1 = and <2 x i8> %x, <i8 poison, i8 3>
195+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8> <i8 1, i8 1>
196+
ret <2 x i8> %cond
197+
}
198+
define <2 x i8> @src_xor_bit_vec_poison2(<2 x i8> %x, <2 x i8> %y) {
199+
; CHECK-LABEL: @src_xor_bit_vec_poison2(
200+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Y:%.*]], <i8 poison, i8 12>
201+
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i8> [[AND]], [[X:%.*]]
202+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[XOR]], <i8 3, i8 3>
203+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 3, i8 3>
204+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
205+
; CHECK-NEXT: ret <2 x i8> [[COND]]
206+
;
207+
%and = and <2 x i8> %y, <i8 poison, i8 12>
208+
%xor = xor <2 x i8> %and, %x
209+
%cmp = icmp eq <2 x i8> %xor, <i8 3, i8 3>
210+
%and1 = and <2 x i8> %x, <i8 3, i8 3>
211+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8> <i8 1, i8 1>
212+
ret <2 x i8> %cond
213+
}
7214

8215
define i32 @and_lshr_and(i32 %arg) {
9216
; CHECK-LABEL: @and_lshr_and(
@@ -590,13 +797,13 @@ define i32 @n5(i32 %arg) {
590797
; CHECK-LABEL: @n5(
591798
; CHECK-NEXT: [[T:%.*]] = and i32 [[ARG:%.*]], 2
592799
; CHECK-NEXT: [[T1:%.*]] = icmp eq i32 [[T]], 0
593-
; CHECK-NEXT: [[T2:%.*]] = and i32 [[ARG]], 2
800+
; CHECK-NEXT: [[T2:%.*]] = and i32 [[ARG]], 3
594801
; CHECK-NEXT: [[T3:%.*]] = select i1 [[T1]], i32 [[T2]], i32 1
595802
; CHECK-NEXT: ret i32 [[T3]]
596803
;
597804
%t = and i32 %arg, 2
598805
%t1 = icmp eq i32 %t, 0
599-
%t2 = and i32 %arg, 2 ; 2 instead of 1
806+
%t2 = and i32 %arg, 3 ; 3 instead of 2
600807
%t3 = select i1 %t1, i32 %t2, i32 1
601808
ret i32 %t3
602809
}

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